UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 562

• Manufacturer Part Number: UPD78F0533AGB-GAH-AX
• Description: MCU 8BIT 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0533AGB-GAH-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 55
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
78K0/Kx2
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
Remark
Condition for clearing (TRC0 = 0)
<Both master and slave>
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When the IICE0 bit changes from 1 to 0 (operation
• Cleared by WREL0 = 1
• When the ALD0 bit changes from 0 to 1 (arbitration
• Reset
• When not used for communication (MSTS0, EXC0,
<Master>
• When “1” is output to the first byte’s LSB (transfer
<Slave>
• When a start condition is detected
• When “0” is input to the first byte’s LSB (transfer direction
Note
Condition for clearing (COI0 = 0)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 changes from 1 to 0 (operation stop)
• Reset
stop)
loss)
COI0 = 0)
direction specification bit)
specification bit)
TRC0
COI0
0
1
0
1
LREL0: Bit 6 of IIC control register 0 (IICC0)
IICE0:
When bit 3 (TRC0) of the IIC status register 0 (IICS0) is set to 1 (transmission status), bit 5 (WREL0) of
the IIC control register 0 (IICC0) is set to 1 during the ninth clock and wait is canceled, after which the
TRC0 bit is cleared (reception status) and the SDAA0 line is set to high impedance. Release the wait
performed while TRC0 bit is 1 (transmission status) by writing to the IIC shift register.
Addresses do not match.
Addresses match.
Receive status (other than transmit status). The SDA0 line is set for high impedance.
Transmit status. The value in the SO0 latch is enabled for output to the SDA0 line (valid starting at the
falling edge of the first byte’s ninth clock).
Bit 7 of IIC control register 0 (IICC0)
Note
Figure 18-6. Format of IIC Status Register 0 (IICS0) (2/3)
(wait cancel)
Detection of transmit/receive status
Detection of matching addresses
Condition for setting (COI0 = 1)
• When the received address matches the local address
Condition for setting (TRC0 = 1)
<Master>
• When a start condition is generated
• When 0 (master transmission) is output to the LSB
<Slave>
• When 1 (slave transmission) is input to the LSB (transfer
(slave address register 0 (SVA0))
(set at the rising edge of the eighth clock).
(transfer direction specification bit) of the first byte
(during address transfer)
direction specification bit) of the first byte from the
master (during address transfer)
CHAPTER 18 SERIAL INTERFACE IIC0
562