UPD78F0533AGB-GAH-AX Renesas Electronics America, UPD78F0533AGB-GAH-AX Datasheet - Page 656

• Manufacturer Part Number: UPD78F0533AGB-GAH-AX
• Description: MCU 8BIT 64-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0/Kx2r

Specifications of UPD78F0533AGB-GAH-AX

• Core Processor: 78K/0
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 55
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0/Kx2
20.4 Interrupt Servicing Operations
20.4.1 Maskable interrupt acknowledgment
corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the
interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged during
servicing of a higher priority interrupt request (when the ISP flag is reset to 0).
Table 20-4 below.
specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same priority
level, the request with the highest default priority is acknowledged first.
the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are
transferred to the ISP flag. The vector table data determined for each interrupt request is the loaded into the PC and
branched.
R01UH0008EJ0401 Rev.4.01
Jul 15, 2010
A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag
The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed in
For the interrupt request acknowledgment timing, see Figures 20-20 and 20-21.
Note If an interrupt request is generated just before a divide instruction, the wait time becomes longer.
Remark 1 clock: 1/f
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 20-19 shows the interrupt request acknowledgment algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC,
Restoring from an interrupt is possible by using the RETI instruction.
Table 20-4. Time from Generation of Maskable Interrupt Until Servicing
CPU
When ××PR = 0
When ××PR = 1
(f
CPU
: CPU clock)
7 clocks
8 clocks
Minimum Time
CHAPTER 20 INTERRUPT FUNCTIONS
32 clocks
33 clocks
Maximum Time
Note
656