MAXQ2010-RFX+ Maxim Integrated Products, MAXQ2010-RFX+ Datasheet - Page 24

• Manufacturer Part Number: MAXQ2010-RFX+
• Description: IC MCU 16BIT 64KB FLASH 100-LQFP
• Manufacturer: Maxim Integrated Products
• Series: MAXQ™r

Specifications of MAXQ2010-RFX+

• Core Processor: RISC
• Core Size: 16-Bit
• Speed: 10MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 55
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Processor Series: MAXQ2010
• Core: RISC
• Data Bus Width: 16 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Controller Family/series: MAXQ
• No. Of I/o's: 43
• Ram Memory Size: 2048Byte
• Cpu Speed: 10MHz
• No. Of Timers: 3
• Embedded Interface Type: I2C, SPI, USART
• Rohs Compliant: Yes
• Number Of Programmable I/os: 55
• Development Tools By Supplier: MAXQ2010-KIT
• Package: 100LQFP
• Family Name: MAXQ
• Maximum Speed: 10 MHz
• On-chip Adc: 8-chx12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16-Bit Mixed-Signal Microcontroller
with LCD Interface
clock source. The device contains an FLL that is used
as a clock source by itself (FLLEN = 0) or as a multipli-
er for the 32kHz crystal (FLLEN = 1). The 32kHz-mode-
based timing is more stable due to the use of the
crystal as a time base.
A crystal warmup counter enhances operational reliabil-
ity. If the user has selected to run from the external
crystal or clock source, each time the external crystal
oscillation must restart, such as after exiting stop mode,
the device initiates a crystal warmup period of 65,536
oscillations. This allows time for the crystal amplitude
and frequency to stabilize before using it as a clock
source. While in the warmup mode, the device operates
from the internal FLL and automatically switches back
to the crystal as soon as it is ready.
Programmable clock-divide control bits (CD1 and CD0)
and the PMME bit provide the processor with the ability
to slow the system clock, resulting in lower power con-
sumption. The CD[1:0] bits default to 00b, selecting a
divide-by-1 system clock, but five clock-divisor options
allow the selection of different crystals to accommodate
specific system needs. In power-management mode
(PMM), one system clock is 256 oscillator cycles, signif-
icantly reducing power consumption while the micro-
controller functions at reduced speed. The switchback
feature allows the system to exit PMM in response to an
external interrupt or serial port activity, quickly switch-
ing from the slower, power-saving mode to full speed.
In addition, the lowest power stop mode allows the
microcontroller to stop the internal oscillator, halting the
system clock.
Multiple interrupt sources are available for quick
response to internal and external events. The MAXQ
architecture uses a single interrupt vector (IV), single
interrupt-service routine (ISR) design. For maximum flex-
ibility, interrupts can be enabled globally, individually, or
by the module. When an interrupt condition occurs, its
individual flag is set, even if the interrupt source is dis-
abled at the local, module, or global level. Interrupt
flags must be cleared within the user-interrupt routine to
avoid repeated interrupts from the same source.
Application software must ensure a delay between the
write to the flag and the RETI instruction to allow time
for the interrupt hardware to remove the internal inter-
rupt condition. Asynchronous interrupt flags require a
one-instruction delay, and synchronous interrupt flags
require a two-instruction delay.
When an enabled interrupt is detected, software jumps
to a user-programmable interrupt vector location. The
IV register defaults to 0000h on reset or power-up, so if
24
______________________________________________________________________________________
Interrupts
it is not changed to a different address, the user pro-
gram must determine whether a jump to 0000h came
from a reset or interrupt source.
Once software control has been transferred to the ISR,
the interrupt identification register (IIR) can be used to
determine if a system register or peripheral register was
the source of the interrupt. The specified module can
then be interrogated for the specific interrupt source and
software can take appropriate action. Because the user
software evaluates the interrupts, the user can define a
unique interrupt priority scheme for each application.
The following interrupt sources are supported:
• Supply Voltage Monitor
• External Interrupts 22 to 0
• Timer 2, 1, 0
• Serial Port 1, 0
• Watchdog Timer
• RTC Time-of-Day or Subsecond Alarm
• SPI
• I
• ADC
When an enabled interrupt is detected, software jumps
to the dedicated interrupt vector address reserved for
that interrupt. User-application code at this address
then routes program execution to a user-defined inter-
rupt routine.
The microcontroller uses Type C and Type D bidirec-
tional I/O pins as described in the MAXQ Family User's
Guide . Each port has up to eight independent, general-
purpose I/O pins and three configure/control registers.
Many pins support alternate functions such as timers or
interrupts, which are enabled, controlled, and monitored
by dedicated peripheral registers. Using the alternate
function automatically converts the pin to that function,
overriding the general-purpose I/O functionality.
Type C port pins have Schmitt trigger receivers and full
CMOS output drivers, and can support alternate func-
tions. The pin is either high impedance or a weak
pullup when defined as an input, dependent on the
state of the corresponding bit in the output register.
Type D port pins have Schmitt trigger receivers and full
CMOS output drivers, and can support alternate func-
tions. The pin is either high impedance or a weak
pullup when defined as an input, dependent on the
state of the corresponding bit in the output register. All
Type D pins also have interrupt capability. See Figure 6
for a Type C/D port pin schematic.
2
C
I/O Ports