MC68HC705KJ1CDW Freescale Semiconductor, MC68HC705KJ1CDW Datasheet - Page 65

• Manufacturer Part Number: MC68HC705KJ1CDW
• Description: IC MCU 4MHZ 1.2K OTP 16-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of MC68HC705KJ1CDW

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 10
• Program Memory Size: 1.2KB (1.2K x 8)
• Program Memory Type: OTP
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

Writing a logic 1 to a DDRA bit enables the output buffer for the corresponding port A pin; a logic 0
disables the output buffer.
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data latch. When bit DDRAx is a logic
0, reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
7.2.3 Pulldown Register A
Pulldown register A inhibits the pulldown devices on port A pins programmed as inputs.
PDIA[7:0] — Pulldown Inhibit A Bits
Freescale Semiconductor
PDIA[7:0] disable the port A pulldown devices. Reset clears PDIA[7:0].
1 = Corresponding port A pulldown device disabled
0 = Corresponding port A pulldown device not disabled
Address:
1. Writing affects the data register but does not affect input.
If the SWPDI bit in the mask option register is programmed to logic 1, reset
initializes all port A pins as inputs with disabled pulldown devices.
Reset:
Read:
Write:
Data Direction Bit
MC68HC705KJ1 • MC68HRC705KJ1 • MC68HLC705KJ1 Data Sheet, Rev. 4.1
READ DDRA
WRITE DDRA
WRITE PORTA
READ PORTA
WRITE PDRA
PDIA7
$0010
Bit 7
0
1
0
= Unimplemented
Figure 7-5. Pulldown Register A (PDRA)
PDIA6
RESET
6
0
Table 7-1. Port A Pin Operation
Figure 7-4. Port A I/O Circuitry
PDIA5
Input, high-impedance
5
0
I/O Pin Mode
DDRAx
PDRAx
PAx
Table 7-1
Output
NOTE
PDIA4
4
0
summarizes the operation of the port A pins.
PDIA3
3
0
SWPDI
Read
Latch
PDIA2
Accesses to Data Bit
Pin
2
0
10-mA SINK CAPABILITY
(PINS PA4–PA7 ONLY)
PDIA1
100-µA
PULLDOWN
1
0
Latch
Write
Latch
PAx
(PA0–PA3 TO
IRQ MODULE)
(1)
PDIA0
Bit 0
0
Port A
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