MC68HC711E9CFU2

Manufacturer Part NumberMC68HC711E9CFU2
DescriptionIC MCU 12K OTP 2MHZ 64-QFP
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E9CFU2 datasheets
 

Specifications of MC68HC711E9CFU2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size12KB (12K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-QFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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10.10 MC68L11E9/E20 Control Timing
Characteristic
Frequency of operation
E-clock period
Crystal frequency
External oscillator frequency
Processor control setup time
t
= 1/4 t
+ 75 ns
PCSU
CYC
Reset input pulse width
To guarantee external reset vector
Minimum input time (can be pre-empted by internal reset)
Mode programming setup time
Mode programming hold time
Interrupt pulse width, IRQ edge-sensitive mode
PW
= t
+ 20 ns
IRQ
CYC
Wait recovery startup time
Timer pulse width input capture pulse accumulator input
PW
= t
+ 20 ns
TIM
CYC
1. V
= 3.0 Vdc to 5.5 Vdc, V
= 0 Vdc, T
DD
SS
otherwise noted
2. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives the pin low for four clock cycles,
releases the pin, and samples the pin level two cycles later to determine the source of the interrupt. Refer to
Resets and Interrupts
for further detail.
(1)
PA[2:0]
(2)
PA[2:0]
(1) (3)
PA7
(2) (3)
PA7
Notes
:
1. Rising edge sensitive input
2. Falling edge sensitive input
3. Maximum pulse accumulator clocking rate is E-clock frequency divided by 2.
Freescale Semiconductor
(1) (2)
Symbol
PW
PW
PW
= T
to T
, all timing is shown with respect to 20% V
A
L
H
PW
TIM
Figure 10-2. Timer Inputs
M68HC11E Family Data Sheet, Rev. 5.1
MC68L11E9/E20 Control Timing
1.0 MHz
2.0 MHz
Min
Max
Min
Max
f
dc
1.0
dc
2.0
o
t
1000
500
CYC
f
4.0
8.0
XTAL
4 f
dc
4.0
dc
8.0
o
t
325
200
PCSU
8
8
RSTL
1
1
t
2
2
MPS
t
10
10
MPH
1020
520
IRQ
t
4
4
WRS
1020
520
TIM
and 70% V
DD
Unit
MHz
ns
MHz
MHz
ns
t
CYC
t
CYC
ns
ns
t
CYC
ns
, unless
DD
Chapter 5
157