MC68HC711E9CFU2

Manufacturer Part NumberMC68HC711E9CFU2
DescriptionIC MCU 12K OTP 2MHZ 64-QFP
ManufacturerFreescale Semiconductor
SeriesHC11
MC68HC711E9CFU2 datasheets
 

Specifications of MC68HC711E9CFU2

Core ProcessorHC11Core Size8-Bit
Speed2MHzConnectivitySCI, SPI
PeripheralsPOR, WDTNumber Of I /o38
Program Memory Size12KB (12K x 8)Program Memory TypeOTP
Eeprom Size512 x 8Ram Size512 x 8
Voltage - Supply (vcc/vdd)4.5 V ~ 5.5 VData ConvertersA/D 8x8b
Oscillator TypeInternalOperating Temperature-40°C ~ 85°C
Package / Case64-QFPLead Free Status / RoHS StatusContains lead / RoHS non-compliant
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3.2.3 Digital Control
All A/D converter operations are controlled by bits in register ADCTL. In addition to selecting the analog
input to be converted, ADCTL bits indicate conversion status and control whether single or continuous
conversions are performed. Finally, the ADCTL bits determine whether conversions are performed on
single or multiple channels.
3.2.4 Result Registers
Four 8-bit registers ADR[4:1] store conversion results. Each of these registers can be accessed by the
processor in the CPU. The conversion complete flag (CCF) indicates when valid data is present in the
result registers. The result registers are written during a portion of the system clock cycle when reads do
not occur, so there is no conflict.
3.2.5 A/D Converter Clocks
The CSEL bit in the OPTION register selects whether the A/D converter uses the system E clock or an
internal RC oscillator for synchronization. When E-clock frequency is below 750 kHz, charge leakage in
the capacitor array can cause errors, and the internal oscillator should be used. When the RC clock is
used, additional errors can occur because the comparator is sensitive to the additional system clock
noise.
3.2.6 Conversion Sequence
A/D converter operations are performed in sequences of four conversions each. A conversion sequence
can repeat continuously or stop after one iteration. The conversion complete flag (CCF) is set after the
fourth conversion in a sequence to show the availability of data in the result registers.
the timing of a typical sequence. Synchronization is referenced to the system E clock.
E CLOCK
12 E CYCLES
SAMPLE ANALOG INPUT
CONVERT FIRST
CHANNEL, UPDATE
0
ADR1
Freescale Semiconductor
MSB
BIT 6
BIT 5
BIT 4
4
2
2
2
CYCLES
CYC
CYC
CYC
SUCCESSIVE APPROXIMATION SEQUENCE
CONVERT SECOND
CONVERT THIRD
CHANNEL, UPDATE
CHANNEL, UPDATE
32
ADR2
64
ADR3
Figure 3-3. A/D Conversion Sequence
M68HC11E Family Data Sheet, Rev. 5.1
Figure 3-3
BIT 3
BIT 2
BIT 1
LSB
2
2
2
2
2
CYC
CYC
CYC
CYC
CYC
END
CONVERT FOURTH
CHANNEL, UPDATE
96
ADR4
128 — E CYCLES
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