MC9S12E256VFUE Freescale Semiconductor, MC9S12E256VFUE Datasheet - Page 114

• Manufacturer Part Number: MC9S12E256VFUE
• Description: IC MCU 256K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256VFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-QFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 12
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• On-chip Dac: 8 bit, 2 Channel
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 50 MHz
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2.4.1.4
The ACCERR flag will be set during the command write sequence if any of the following illegal steps are
performed, causing the command write sequence to immediately abort:
The ACCERR flag will not be set if any Flash register is read during a valid command write sequence.
The ACCERR flag will also be set if any of the following events occur:
If the Flash memory is read during execution of an algorithm (i.e., CCIF flag in the FSTAT register is low),
the read operation will return invalid data and the ACCERR flag will not be set.
If the ACCERR flag is set in the FSTAT register, the user must clear the ACCERR flag before starting
another command write sequence (see
The PVIOL flag will be set after the command is written to the FCMD register during a command write
sequence if any of the following illegal operations are attempted, causing the command write sequence to
immediately abort:
114
1. Writing to a Flash address before initializing the FCLKDIV register.
2. Writing to a Flash address in the range 0x8000–0xBFFF when the PPAGE register does not select
3. Writing to a Flash address in the range 0x4000–0x7FFF or 0xC000–0xFFFF with the BKSEL bit
4. Writing a byte or misaligned word to a valid Flash address.
5. Starting a command write sequence while a data compress operation is active.
6. Starting a command write sequence while a sector erase abort operation is active.
7. Writing a second word to a Flash address in the same command write sequence.
8. Writing to any Flash register other than FCMD after writing a word to a Flash address.
9. Writing a second command to the FCMD register in the same command write sequence.
10. Writing an invalid command to the FCMD register.
11. When security is enabled, writing a command other than mass erase to the FCMD register when
12. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD
13. Writing a 0 to the CBEIF flag in the FSTAT register to abort a command write sequence.
1. Launching the sector erase abort command while a sector erase operation is active which results in
2. The MCU enters stop mode and a program or erase operation is in progress. The operation is
1. Writing the program command if the address written in the command write sequence was in a
2. Writing the sector erase command if the address written in the command write sequence was in a
3. Writing the mass erase command while any Flash protection is enabled.
a 16 Kbyte page in the Flash block selected by the BKSEL bit in the FCNFG register.
in the FCNFG register not selecting Flash block 0.
the write originates from a non-secure memory location or from the Background Debug Mode.
register.
the early termination of the sector erase operation (see
Command”)
aborted immediately and any pending command is purged (see
protected area of the Flash memory.
protected area of the Flash memory.
Illegal Flash Operations
MC9S12E256 Data Sheet, Rev. 1.08
Section 2.3.2.7, “Flash Status Register
Section 2.4.1.3.6, “Sector Erase Abort
Section 2.5.2, “Stop
(FSTAT)”).
Freescale Semiconductor
Mode”).