MC9S12E256VFUE Freescale Semiconductor, MC9S12E256VFUE Datasheet - Page 65

IC MCU 256K FLASH 25MHZ 80-QFP

MC9S12E256VFUE

Manufacturer Part Number
MC9S12E256VFUE
Description
IC MCU 256K FLASH 25MHZ 80-QFP
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet

Specifications of MC9S12E256VFUE

Core Processor
HCS12
Core Size
16-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
60
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.35 V ~ 2.75 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
80-QFP
Processor Series
S12E
Core
HCS12
Data Bus Width
16 bit
Data Ram Size
16 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
60
Number Of Timers
12
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWHCS12
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
On-chip Dac
8 bit, 2 Channel
Package
80PQFP
Family Name
HCS12
Maximum Speed
50 MHz
For Use With
M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9S12E256VFUE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
1.4.19
PAD[15:0] are the analog inputs for the analog to digital converter (ADC). They can also be configured as
general purpose digital input or output pin. When enabled as digital inputs or outputs, the PAD[15:0] can
also be configured as Keypad Wake-up pins (KWU) and generate interrupts causing the MCU to exit
STOP or WAIT mode. Consult
“Analog-to-Digital Converter (ATD10B16CV4)”
1.4.20
PM7 is a general purpose input or output pin. When the IIC module is enabled it becomes the serial clock
line (SCL) for the IIC module (IIC). While in reset and immediately out of reset the PM7 pin is configured
as a high impedance input pin. Consult
Chapter 10, “Inter-Integrated Circuit (IICV2)”
1.4.21
PM6 is a general purpose input or output pin. When the IIC module is enabled it becomes the Serial Data
Line (SDL) for the IIC module (IIC). While in reset and immediately out of reset the PM6 pin is configured
as a high impedance input pin. Consult
Chapter 10, “Inter-Integrated Circuit (IICV2)”
1.4.22
PM5 is a general purpose input or output. When the Serial Communications Interface 2 (SCI2) transmitter
is enabled the PM5 pin is configured as the transmit pin TXD2 of SCI2. While in reset and immediately
out of reset the PM5 pin is configured as a high impedance input pin. Consult
Module (PIM9E256V1)”
about pin configurations.
1.4.23
PM4 is a general purpose input or output. When the Serial Communications Interface 2 (SCI2) receiver is
enabled the PM4 pin is configured as the receive pin RXD2 of SCI2. While in reset and immediately out
of reset the PM4 pin is configured as a high impedance input pin. Consult
Module (PIM9E256V1)”
about pin configurations.
1.4.24
PM3 is a general purpose input or output pin. While in reset and immediately out of reset the PM3 pin is
configured as a high impedance input pin. Consult
for information about pin configurations.
Freescale Semiconductor
PAD[15:0] / AN[15:0] / KWAD[15:0] — Port AD I/O Pins [15:0]
PM7 / SCL — Port M I/O Pin 7
PM6 / SDA — Port M I/O Pin 6
PM5 / TXD2 — Port M I/O Pin 5
PM4 / RXD2 — Port M I/O Pin 4
PM3 — Port M I/O Pin 3
and
and
Chapter 8, “Serial Communication Interface (SCIV4)”
Chapter 8, “Serial Communication Interface (SCIV4)”
Chapter 3, “Port Integration Module (PIM9E256V1)”
MC9S12E256 Data Sheet, Rev. 1.08
Chapter 3, “Port Integration Module (PIM9E256V1)”
Chapter 3, “Port Integration Module (PIM9E256V1)”
for information about pin configurations.
for information about pin configurations.
for information about pin configurations.
Chapter 3, “Port Integration Module (PIM9E256V1)”
Chapter 1 MC9S12E256 Device Overview (MC9S12E256DGV1)
Chapter 3, “Port Integration
Chapter 3, “Port Integration
for information
for information
and the
Chapter 6,
and
and
65

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