MC9S12E256VFUE Freescale Semiconductor, MC9S12E256VFUE Datasheet - Page 461

• Manufacturer Part Number: MC9S12E256VFUE
• Description: IC MCU 256K FLASH 25MHZ 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12E256VFUE

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.75 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 80-QFP
• Processor Series: S12E
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 60
• Number Of Timers: 12
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• On-chip Dac: 8 bit, 2 Channel
• Package: 80PQFP
• Family Name: HCS12
• Maximum Speed: 50 MHz
• For Use With: M68EVB912E128 - BOARD EVAL FOR MC9S12E128/64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

15.4.7
BDM commands that require CPU execution are ultimately treated at the MCU bus rate. Because the BDM
clock source can be asynchronously related to the bus frequency, when CLKSW = 0, it is very helpful to
provide a handshake protocol in which the host could determine when an issued command is executed by
the CPU. The alternative is to always wait the amount of time equal to the appropriate number of cycles
at the slowest possible rate the clock could be running. This sub-section will describe the hardware
handshake protocol.
The hardware handshake protocol signals to the host controller when an issued command was successfully
executed by the target. This protocol is implemented by a 16 serial clock cycle low pulse followed by a
brief speedup pulse in the BKGD pin. This pulse is generated by the target MCU when a command, issued
by the host, has been successfully executed (see
After the ACK pulse has finished: the host can start the bit retrieval if the last issued command was a read
command, or start a new command if the last command was a write command or a control command
(BACKGROUND, GO, GO_UNTIL, or TRACE1). The ACK pulse is not issued earlier than 32 serial
clock cycles after the BDM command was issued. The end of the BDM command is assumed to be the
16th tick of the last bit. This minimum delay assures enough time for the host to perceive the ACK pulse.
Note also that, there is no upper limit for the delay between the command and the related ACK pulse,
because the command execution depends upon the CPU bus frequency, which in some cases could be very
slow compared to the serial communication rate. This protocol allows a great flexibility for the POD
designers, because it does not rely on any accurate time measurement or short response time to any event
in the serial communication.
Freescale Semiconductor
(TARGET MCU)
ACK
TRANSMITS
BDM CLOCK
BKGD PIN
TARGET
PULSE
16th TICK OF THE
LAST COMMAD BIT
Serial Interface Hardware Handshake Protocol
If the ACK pulse was issued by the target, the host assumes the previous
command was executed. If the CPU enters WAIT or STOP prior to
executing a hardware command, the ACK pulse will not be issued meaning
that the BDM command was not executed. After entering wait or stop mode,
the BDM command is no longer pending.
HIGH-IMPEDANCE
32 CYCLES
Figure 15-10. Target Acknowledge Pulse (ACK)
MC9S12E256 Data Sheet, Rev. 1.08
MINIMUM DELAY
FROM THE BDM COMMAND
Figure
NOTE
16 CYCLES
15-10). This pulse is referred to as the ACK pulse.
SPEEDUP PULSE
Chapter 15 Background Debug Module (BDMV4)
EARLIEST
START OF
NEXT BIT
HIGH-IMPEDANCE
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