CA3130EZ Intersil, CA3130EZ Datasheet - Page 10

• Manufacturer Part Number: CA3130EZ
• Description: IC OP AMP 15MHZ BIMOS 8-DIP
• Manufacturer: Intersil

Specifications of CA3130EZ

• Amplifier Type: General Purpose
• Number Of Circuits: 1
• Slew Rate: 30 V/µs
• Gain Bandwidth Product: 15MHz
• Current - Input Bias: 5pA
• Voltage - Input Offset: 8000µV
• Current - Supply: 10mA
• Current - Output / Channel: 45mA
• Voltage - Supply, Single/dual (±): 5 V ~ 16 V, ±2.5 V ~ 8 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Bandwidth: 15 MHz
• Common Mode Rejection Ratio: 90
• Current, Input Bias: 0.000005 μA
• Current, Input Offset: 0.5 pA
• Current, Output: 22 mA
• Current, Supply: 10 mA
• Number Of Amplifiers: Single
• Package Type: PDIP-8
• Resistance, Input: 1.5 Teraohms
• Temperature, Operating, Range: -55 to +125 °C
• Time, Rise: 0.09 μs
• Voltage, Gain: 320 kV/V
• Voltage, Input: -0.5 to 23 V
• Voltage, Noise: 23000 nV/sqrt Hz
• Voltage, Offset: 8 mV
• Voltage, Output, High: 13.3 V
• Voltage, Output, Low: 0.002 V
• Voltage, Supply: 5 to 16 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Gain =
20V
1V
R
R
+
3
3
+15V
-
P-P
= 4kΩ
P-P
= R
2µF
25V
R
------ - = X =
R
FIGURE 11. SINGLE SUPPLY, ABSOLUTE VALUE, IDEAL FULL-WAVE RECTIFIER WITH ASSOCIATED WAVEFORMS
Input: BW(-3dB) = 130kHz, DC Output (Avg) = 160mV
+10.010V
1
Input: BW(-3dB) = 230kHz, DC Output (Avg) = 3.2V
2
1
REGULATOR




X + X
------------------
VOLTAGE
0.75
---------- -
1 - X
0.5
9
7
4
2
3
 = 6kΩ

LSB
4kΩ
R
-------------------------------------
R
2
13
6
8
9
4


1
CA3085
1
“SWITCHES”
806K
1%
806K
1%
+ R
CD4007A
0.001µF
7
R
3
2
8
3
1
5
1
6
For X = 0.5:
+ R
20pF
402K
1%
62
2
3
10
3
2kΩ
R
8
10
12
FIGURE 10. 9-BIT DAC USING CMOS DIGITAL SWITCHES AND CA3130
7
2
8
CA3130
22.1k
1%
1K
3.83k
1%
+10.010V
+
-
200K
1%
1
14
11
2
REGULATED
2KΩ
----------- - =
4kΩ
5
VOLTAGE
OFFSET
ADJUST
100kΩ
7
4
ADJ
10V LOGIC INPUTS
13
+15V
6
6
8
“SWITCHES”
100K
1%
R
------ -
R
806K
1%
6
CD4007A
2
1
OUTPUT
0.01
µF
1N914
LOAD
5
3
1
5
R
3
750K
1%
806K
CA3130, CA3130A
806K
1%
1%
10
12
4
6
5.1kΩ
806K
1%
ADJUST
PEAK
2kΩ
OFFSET
100K
NULL
13
3
6
8
4
“SWITCHES”
PARALLELED
806K
1%
RESISTORS
0.1µF
(2)
CA3130
CD4007A
5
2K
7
1
2
3
1
5
+15V
+
-
806K
1%
8
(4)
56pF
MSB
10
12
3
2
VOLTAGE
FOLLOWER
1
806K
1%
(8)
Time base on both traces: 0.2ms/Div.
Bottom Trace: Input Signal; 10V/Div.
10K
Top Trace: Output Signal; 2V/Div.
NOTE: All resistances are in ohms.
6 - 9
BIT
1
2
3
4
5
RATIO-MATCH
STANDARD
±0.1%
±0.2%
±0.4%
±0.8%
±1% ABS
REQUIRED
0V
0V