CA3130EZ Intersil, CA3130EZ Datasheet - Page 7

• Manufacturer Part Number: CA3130EZ
• Description: IC OP AMP 15MHZ BIMOS 8-DIP
• Manufacturer: Intersil

Specifications of CA3130EZ

• Amplifier Type: General Purpose
• Number Of Circuits: 1
• Slew Rate: 30 V/µs
• Gain Bandwidth Product: 15MHz
• Current - Input Bias: 5pA
• Voltage - Input Offset: 8000µV
• Current - Supply: 10mA
• Current - Output / Channel: 45mA
• Voltage - Supply, Single/dual (±): 5 V ~ 16 V, ±2.5 V ~ 8 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Bandwidth: 15 MHz
• Common Mode Rejection Ratio: 90
• Current, Input Bias: 0.000005 μA
• Current, Input Offset: 0.5 pA
• Current, Output: 22 mA
• Current, Supply: 10 mA
• Number Of Amplifiers: Single
• Package Type: PDIP-8
• Resistance, Input: 1.5 Teraohms
• Temperature, Operating, Range: -55 to +125 °C
• Time, Rise: 0.09 μs
• Voltage, Gain: 320 kV/V
• Voltage, Input: -0.5 to 23 V
• Voltage, Noise: 23000 nV/sqrt Hz
• Voltage, Offset: 8 mV
• Voltage, Output, High: 13.3 V
• Voltage, Output, Low: 0.002 V
• Voltage, Supply: 5 to 16 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

o
Power-Supply Considerations
Because the CA3130 is very useful in single-supply
applications, it is pertinent to review some considerations
relating to power-supply current consumption under both
single-and dual-supply service. Figures 6A and 6B show the
CA3130 connected for both dual-and single-supply
operation.
Dual-supply Operation: When the output voltage at Terminal
6 is 0V, the currents supplied by the two power supplies are
equal. When the gate terminals of Q
increasingly positive with respect to ground, current flow
through Q
FIGURE 5. TYPICAL INCREMENTAL OFFSET-VOLTAGE
FIGURE 6. CA3130 OUTPUT STAGE IN DUAL AND SINGLE
7
6
5
4
3
2
1
0
FIGURE 6B. SINGLE POWER SUPPLY OPERATION
FIGURE 6A. DUAL POWER SUPPLY OPERATION
0
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 2V
OUTPUT STAGE TOGGLED
12
3
2
3
2
500
SHIFT vs OPERATING LIFE
POWER SUPPLY OPERATION
(from the negative supply) to the load is
DIFFERENTIAL DC VOLTAGE
(ACROSS TERMINALS 2 AND 3) = 0V
OUTPUT VOLTAGE = V+ / 2
1000
CA3130
CA3130
+
+
-
-
8
8
1500
V+
TIME (HOURS)
T
7
4
7
4
A
2000 2500
Q
Q
Q
Q
V-
7
8
12
8
12
= 125
V+
o
C FOR TO-5 PACKAGES
8
and Q
3000 3500
6
6
12
are driven
R
R
L
L
CA3130, CA3130A
4000
increased and current flow through Q
supply) decreases correspondingly. When the gate terminals
of Q
to ground, current flow through Q
flow through Q
Single-supply Operation: Initially, let it be assumed that the
value of R
terminal bias (Terminals 2 and 3) is such that the output
terminal (No. 6) voltage is at V+/2, i.e., the voltage drops
across Q
typical quiescent supply-current vs supply-voltage for the
CA3130 operated under these conditions. Since the output
stage is operating as a Class A amplifier, the supply-current
will remain constant under dynamic operating conditions as
long as the transistors are operated in the linear portion of
their voltage-transfer characteristics (see Figure 2). If either
Q
(a non-linear region), there will be a corresponding reduction
in supply-current. In the extreme case, e.g., with Terminal 8
swung down to ground potential (or tied to ground), NMOS
transistor Q
series-connected transistors Q
The two preceding stages in the CA3130, however, continue
to draw modest supply-current (see the lower curve in Figure
20) even though the output stage is strobed off. Figure 6A
shows a dual-supply arrangement for the output stage that
can also be strobed off, assuming R
potential of Terminal 8 down to that of Terminal 4.
Let it now be assumed that a load-resistance of nominal
value (e.g., 2kΩ) is connected between Terminal 6 and
ground in the circuit of Figure 6B. Let it be assumed again
that the input-terminal bias (Terminals 2 and 3) is such that
the output terminal (No. 6) voltage is at V+/2. Since PMOS
transistor Q
and transistor Q
conditions the supply-current must increase as an inverse
function of the R
drop across PMOS transistor Q
current at several supply voltages. Figure 2 shows the
voltage-transfer characteristics of the output stage for
several values of load resistance.
Wideband Noise
From the standpoint of low-noise performance
considerations, the use of the CA3130 is most advantageous
in applications where in the source resistance of the input
signal is on the order of 1MΩ or more. In this case, the total
input-referred noise voltage is typically only 23µV when the
test-circuit amplifier of Figure 7 is operated at a total supply
voltage of 15V. This value of total input-referred noise
remains essentially constant, even though the value of
source resistance is raised by an order of magnitude. This
characteristic is due to the fact that reactance of the input
capacitance becomes a significant factor in shunting the
source resistance. It should be noted, however, that for
8
or Q
8
and Q
12
8
L
and Q
are swung out of their linear regions toward cut-off
12
is very high (or disconnected), and that the input-
8
12
must now supply quiescent current to both R
is completely cut off and the supply-current to
12
are driven increasingly negative with respect
12
L
12
is decreased accordingly.
magnitude. Figure 22 shows the voltage-
, it should be apparent that under these
are of equal magnitude. Figure 20 shows
8
, Q
8
8
as a function of load
12
is increased and current
L
goes essentially to zero.
= ∞ by pulling the
8
(from the positive
L