CA3130EZ Intersil, CA3130EZ Datasheet - Page 4

• Manufacturer Part Number: CA3130EZ
• Description: IC OP AMP 15MHZ BIMOS 8-DIP
• Manufacturer: Intersil

Specifications of CA3130EZ

• Amplifier Type: General Purpose
• Number Of Circuits: 1
• Slew Rate: 30 V/µs
• Gain Bandwidth Product: 15MHz
• Current - Input Bias: 5pA
• Voltage - Input Offset: 8000µV
• Current - Supply: 10mA
• Current - Output / Channel: 45mA
• Voltage - Supply, Single/dual (±): 5 V ~ 16 V, ±2.5 V ~ 8 V
• Operating Temperature: -55°C ~ 125°C
• Mounting Type: Through Hole
• Package / Case: 8-DIP (0.300", 7.62mm)
• Bandwidth: 15 MHz
• Common Mode Rejection Ratio: 90
• Current, Input Bias: 0.000005 μA
• Current, Input Offset: 0.5 pA
• Current, Output: 22 mA
• Current, Supply: 10 mA
• Number Of Amplifiers: Single
• Package Type: PDIP-8
• Resistance, Input: 1.5 Teraohms
• Temperature, Operating, Range: -55 to +125 °C
• Time, Rise: 0.09 μs
• Voltage, Gain: 320 kV/V
• Voltage, Input: -0.5 to 23 V
• Voltage, Noise: 23000 nV/sqrt Hz
• Voltage, Offset: 8 mV
• Voltage, Output, High: 13.3 V
• Voltage, Output, Low: 0.002 V
• Voltage, Supply: 5 to 16 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

Schematic Diagram
NOTE:
Application Information
Circuit Description
Figure 1 is a block diagram of the CA3130 Series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5V below the negative supply rail, and the output
can be swung very close to either supply rail in many
applications. Consequently, the CA3130 Series circuits are
ideal for single-supply operation. Three Class A amplifier
stages, having the individual gain capability and current
consumption shown in Figure 1, provide the total gain of the
CA3130. A biasing circuit provides two potentials for
common use in the first and second stages.
Terminal 8 can be used both for phase compensation and to
strobe the output stage into quiescence. When Terminal 8 is
tied to the negative supply rail (Terminal 4) by mechanical or
electrical means, the output potential at Terminal 6
essentially rises to the positive supply-rail potential at
Terminal 7. This condition of essentially zero current drain in
5. Diodes D
INV.-INPUT
BIAS CIRCUIT
NON-INV.
INPUT
40kΩ
Z
8.3V
5
R
1
3
2
through D
1
+
-
5kΩ
R
2
D
D
D
D
1
2
3
4
Q
8
1
provide gate-oxide protection for MOSFET input stage.
INPUT STAGE
D
4
5
Q
5
Q
6
CURRENT SOURCE FOR
1kΩ
1kΩ
D
2
R
R
6
Q
3
5
4
OFFSET NULL
Q
Q
6
9
(NOTE 5)
AND Q
1kΩ
Q
R
10
6
7
D
R
1kΩ
7
4
Q
CA3130, CA3130A
7
1
D
8
COMPENSATION
“CURRENT SOURCE
SECOND
STAGE
LOAD” FOR Q
Q
3
Q
Q
5
the output stage under the strobed “OFF” condition can only
be achieved when the ohmic load resistance presented to
the amplifier is very high (e.g.,when the amplifier output is
used to drive CMOS digital circuits in Comparator
applications).
Input Stage
The circuit of the CA3130 is shown in the schematic diagram.
It consists of a differential-input stage using PMOS field-effect
transistors (Q
transistors (Q
with resistors R
The mirror-pair transistors also function as a differential-to-
single-ended converter to provide base drive to the second-
stage bipolar transistor (Q
can be effected by connecting a 100,000Ω potentiometer
across Terminals 1 and 5 and the potentiometer slider arm to
Terminal 4.
11
11
6
9
, Q
, Q
3
8
through R
7
10
OUTPUT
STAGE
) working into a mirror-pair of bipolar
) functioning as load resistors together
STROBING
11
6
.
). Offset nulling, when desired,
Q
Q
8
12
7
4
V+
V-
OUTPUT
6