XC56309VL100A Freescale Semiconductor, XC56309VL100A Datasheet - Page 104

IC DSP 24BIT 100MHZ 196-MAPBGA

XC56309VL100A

Manufacturer Part Number
XC56309VL100A
Description
IC DSP 24BIT 100MHZ 196-MAPBGA
Manufacturer
Freescale Semiconductor
Series
DSP563xxr
Type
Fixed Pointr
Datasheets

Specifications of XC56309VL100A

Interface
Host Interface, SSI, SCI
Clock Rate
100MHz
Non-volatile Memory
ROM (576 B)
On-chip Ram
24kB
Voltage - I/o
3.30V
Voltage - Core
3.30V
Operating Temperature
-40°C ~ 100°C
Mounting Type
Surface Mount
Package / Case
196-MAPBGA
Device Core Size
24b
Format
Fixed Point
Clock Freq (max)
100MHz
Mips
100
Device Input Clock Speed
100MHz
Ram Size
102KB
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (min)
3V
Operating Supply Voltage (max)
3.6V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
196
Package Type
MA-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC56309VL100A
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
XC56309VL100AR2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Host Interface (HI08)
6.3 Overview
The HI08 is partitioned into two register banks, as Figure 6-1 shows. The host-side register bank
is accessible only to the host, and the DSP-side register bank is accessible only to the DSP core.
For the host, the HI08 appears as eight byte-wide locations mapped in its external address space.
The DSP-side registers appear to the DSP core as six 24-bit registers mapped into internal I/O X
memory space and therefore accessible via standard DSP56300 instructions and addressing
modes.
6-4
HCR
ISR
8
24
Control Registers
ISR = Interface Status Register
ICR = Interface Control Register
CVR = Command Vector Register
IVR = Interrupt Vector Register
Control Registers
HCR = Host Control Register
HSR = Host Status Register
HPCR = Host Port Control Register
HBAR = Host Base Address Register
HSR
ICR
24
8
HDDR
CVR
8
24
Figure 6-1. HI08 Block Diagram
HDR
IVR
DSP-Side Registers
DSP56309 User’s Manual, Rev. 1
DSP Peripheral Data Bus
8
24
Core DMA Data Bus
3
Host-Side Registers
Comparator
HBAR
Latch
Address
HOST Bus
8
24
5
3
Data Registers
HTX = Host Transmit Register
HRX = Host Receive Register
HDDR = Host Data Direction Register
HDR = Host Data Register
Data Registers
RXH = Receive Register High
RXM = Receive Register Middle
RXL = Receive Register Low
TXH = Transmit Register High
TXM = Transmit Register Middle
TXL = Transmit Register Low
RXH
24
HPCR
8
RXM
8
24
RXL
HTX
8
24
24
TXH
24
8
HRX
TXM
Freescale Semiconductor
8
24
24
TXL
8
DSP
Side
Host
Side

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