TMPM362F10FG Toshiba, TMPM362F10FG Datasheet
TMPM362F10FG
Specifications of TMPM362F10FG
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TMPM362F10FG Summary of contents
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... Bit RISC Microcontroller TX03 Series TMPM362F10FG ...
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... TOSHIBA CORPORATION All Rights Reserved ...
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... ARM, ARM Powered, AMBA, ADK, ARM9TDMI, TDMI, PrimeCell, RealView, Thumb, Cortex, Coresight, ARM9, ARM926EJ-S, Embedded Trace Macrocell, ETM, AHB, APB, and KEIL are registered trademarks or trademarks of ARM Limited in the EU and other countries. ************************************************************************************************************************* TMPM362F10FG R ...
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... This register does not exist in this microcontroller. b. SFR(register) ・ Each register basically consists of a 32-bit register (some exceptions). ・ The description of each register provides bits, bit symbols, types, initial values after reset and func- tions. Register name SAMCR TMPM362F10FG Base Address = 0x0000_0000 Address(Base+) 0x0004 0x000C ...
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... Register name <Bit Symbol> Exmaple: SAMCR<MODE>="000" or SAMCR<MODE[2:0]>="000" <MODE[2:0]> indicates bit 2 to bit 0 in bit symbol mode (3bit width). ・ Register name [Bit] Example: SAMCR[9:7]="000" It indicates bit 9 to bit 7 of the register SAMCR (32 bit width TDATA Function READ WRITE TMPM362F10FG MODE ...
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... TMPM362F10FG ...
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Date Revision 2011/6/21 1 Revision History Comment First Release ...
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...
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... Exclusive access......................................................................................................................19 3. Debug Interface 3.1 Specification Overview...........................................................................................................21 3.2 SW-DP.....................................................................................................................................21 3.3 ETM.........................................................................................................................................21 3.4 Pin functions............................................................................................................................22 3.5 Peripheral Functions in Halt Mode.........................................................................................23 3.6 Connection with a Debug Tool...............................................................................................23 4. Memory Map 4.1 Memory Map...........................................................................................................................25 4.1.1 Memory map of the TMPM362F10FG............................................................................................................................26 4.2 SFR area detail........................................................................................................................27 i ...
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Reset 5.1 Cold reset.................................................................................................................................29 5.2 Warm reset...............................................................................................................................31 5.2.1 Reset period.......................................................................................................................................................................31 5.3 After reset................................................................................................................................31 6. Clock / Mode Control 6.1 Features....................................................................................................................................33 6.2 Registers..................................................................................................................................34 6.2.1 Register List.......................................................................................................................................................................34 6.2.2 CGSYSCR (System control register)................................................................................................................................35 6.2.3 CGOSCCR (Oscillation control register).........................................................................................................................37 6.2.4 CGSTBYCR (Standby control ...
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Exception exit 7.2 Reset Exceptions.....................................................................................................................68 7.3 Non-Maskable Interrupts (NMI).............................................................................................68 7.4 SysTick....................................................................................................................................68 7.5 Interrupts..................................................................................................................................69 7.5.1 Interrupt Sources................................................................................................................................................................69 7.5.1.1 Interrupt route 7.5.1.2 Generation 7.5.1.3 Transmission 7.5.1.4 Precautions when using external interrupt pins 7.5.1.5 List of Interrupt Sources 7.5.1.6 Active level 7.5.2 ...
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PACR (Port A output control register) 8.2.1.5 PAFR1 (Port A function register 1) 8.2.1.6 PAOD (Port A open drain control register) 8.2.1.7 PAPUP (Port A pull-up control register) 8.2.1.8 PAIE (Port A input control register) 8.2.2 Port B (PB0 ...
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PHIE (Port H input control register) 8.2.9 Port I (PI0 to PI3)............................................................................................................................................................173 8.2.9.1 Port I Circuit Type 8.2.9.2 Port I register 8.2.9.3 PIDATA (Port I data register) 8.2.9.4 PICR (Port I output control register) 8.2.9.5 PIFR1 (Port I function ...
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PPIE (Port P input control register) 8.3 Block Diagrams of Ports.......................................................................................................217 8.3.1 Port Types........................................................................................................................................................................217 8.3.2 Type T1............................................................................................................................................................................219 8.3.3 Type T2............................................................................................................................................................................220 8.3.4 Type T3............................................................................................................................................................................221 8.3.5 Type T4............................................................................................................................................................................222 8.3.6 Type T5............................................................................................................................................................................223 8.3.7 Type T6............................................................................................................................................................................224 8.3.8 Type T7............................................................................................................................................................................225 8.3.9 Type T8............................................................................................................................................................................226 8.3.10 ...
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Block diagram.......................................................................................................................277 9.4 Description of Registers........................................................................................................278 9.4.1 DMAC register list..........................................................................................................................................................278 9.4.2 DMACIntStatus (DMAC Interrupt Status Register)......................................................................................................279 9.4.3 DMACIntTCStatus (DMAC Interrupt Terminal Count Status Register)......................................................................280 9.4.4 DMACIntTCClear (DMAC Interrupt Terminal Count Clear Register).........................................................................281 9.4.5 DMACIntErrorStatus (DMAC Interrupt Error Status Register)....................................................................................282 ...
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Registers..............................................................................................................................332 11.4.1 Register list according to channel.................................................................................................................................332 11.4.2 TBxEN (Enable register)...............................................................................................................................................333 11.4.3 TBxRUN (RUN register)..............................................................................................................................................334 11.4.4 TBxCR (Control register)..............................................................................................................................................335 11.4.5 TBxMOD (Mode register).............................................................................................................................................336 11.4.6 TBxFFCR (Flip-flop control register)...........................................................................................................................338 11.4.7 TBxST (Status register).................................................................................................................................................339 11.4.8 TBxIM (Interrupt mask register)...................................................................................................................................340 11.4.9 TBxUC ...
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Clock Control......................................................................................................................383 12.7.1 Prescaler.........................................................................................................................................................................383 12.7.2 Serial Clock Generation Circuit....................................................................................................................................389 12.7.2.1 Baud Rate Generator 12.7.2.2 Clock Selection Circuit 12.8 Transmit / Receive Buffer and FIFO..................................................................................393 12.8.1 Configuration.................................................................................................................................................................393 12.8.2 Transmit / Receive Buffer.............................................................................................................................................393 12.8.3 FIFO...............................................................................................................................................................................393 12.9 Status Flag...........................................................................................................................394 12.10 Error Flag...........................................................................................................................394 ...
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Register List...................................................................................................................................................................425 13.3.2 SSPCR0(Control register 0)..........................................................................................................................................426 13.3.3 SSPCR1(Control register1)...........................................................................................................................................427 13.3.4 SSPDR(Data register)....................................................................................................................................................428 13.3.5 SSPSR(Status register)..................................................................................................................................................429 13.3.6 SSPCPSR (Clock prescale register)..............................................................................................................................430 13.3.7 SSPIMSC (Interrupt enable/disable register)................................................................................................................431 13.3.8 SSPRIS (Pre-enable interrupt status register)...............................................................................................................432 13.3.9 SSPMIS (Post-enable interrupt status register)............................................................................................................433 13.3.10 SSPICR ...
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Master mode 14.6.2.2 Slave mode 14.6.3 Transferring a Data Word.............................................................................................................................................467 14.6.3.1 Master mode (<MST> = "1") 14.6.3.2 Slave mode (<MST> = "0") 14.6.4 Generating the Stop Condition......................................................................................................................................472 14.6.5 Restart Procedure...........................................................................................................................................................472 14.7 Control register of SIO mode..............................................................................................474 14.7.1 SBIxCR0(control register ...
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Remote control signal preprocessor(RMC) 16.1 Basic operation....................................................................................................................523 16.1.1 Reception of Remote Control Signal............................................................................................................................523 16.2 Block Diagram.....................................................................................................................523 16.3 Registers..............................................................................................................................524 16.3.1 Register List...................................................................................................................................................................524 16.3.2 RMCxEN(Enable Register)...........................................................................................................................................525 16.3.3 RMCxREN(Receive Enable Register)..........................................................................................................................526 16.3.4 RMCxRBUF1(Receive Data Buffer Register 1)..........................................................................................................527 16.3.5 RMCxRBUF2(Receive Data Buffer Register ...
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Register in detail..................................................................................................................556 18.3.1 Register list....................................................................................................................................................................556 18.3.2 KWUPCR0 (Control register 0)....................................................................................................................................556 18.3.3 KWUPCR1 (Control register 1)....................................................................................................................................557 18.3.4 KWUPCR2 (Control register 2)....................................................................................................................................558 18.3.5 KWUPCR3 (Control register 3)....................................................................................................................................559 18.3.6 KWUPPKEY (Port monitor register)...........................................................................................................................560 18.3.7 KWUPCNT (Pull-up cycle register).............................................................................................................................561 18.3.8 KWUPCLR (All ...
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Starting AD Conversion 20.4.5.2 AD Conversion 20.4.5.3 Top-priority AD conversion during normal AD conversion 20.4.5.4 Stopping Repeat Conversion Mode 20.4.5.5 Reactivating normal AD conversion 20.4.5.6 Conversion completion 20.4.5.7 Interrupt generation timings and AD conversion result storage register 21. Real ...
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Determination of a Serial Operation Mode 22.2.10.7 Password 22.2.10.8 Calculation of the Show Flash Memory Sum Command 22.2.10.9 Checksum Calculation 22.2.11 General Boot Program Flowchart...............................................................................................................................663 22.3 On-board Programming of Flash Memory (Rewrite/Erase)...............................................664 22.3.1 Flash Memory................................................................................................................................................................664 22.3.1.1 Block Configuration 22.3.1.2 ...
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SCOUT Pin AC Characteristic...................................................................................................................................708 25.6.11 Debug communication.................................................................................................................................................709 25.6.12 ETM Trace...................................................................................................................................................................710 25.7 Flash Characteristics............................................................................................................710 25.7.1 Erase / Write Characteristics.........................................................................................................................................710 25.8 Oscillation Circuit...............................................................................................................711 25.8.1 Ceramic oscillator..........................................................................................................................................................711 25.8.2 Crystal oscillator............................................................................................................................................................711 25.9 Handling Precaution............................................................................................................712 25.9.1 Solderability...................................................................................................................................................................712 25.9.2 Power-on sequence........................................................................................................................................................712 26. Port Section Equivalent ...
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... TMPM362F10FG The TMPM362F10FG is a 32-bit RISC microprocessor series with an ARM Cortex-M3 microprocessor core. Product name TMPM362F10FG Features of the TMPM362F10FG are as follows : 1.1 Features 1. ARM Cortex-M3 microprocessor core a. Improved code efficiency has been realized through the use of Thumb-2 instruction. ・ New 16-bit Thumb instructions for improved program flow ・ ...
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... Conversion speed 1.15 μsec (@ fsys = 40 MHz) 14. Key-on wake-up (KWUP channels Dynamic pull-up 15. BACKUP module (BUPMD) Low power consumption can be realized by shutdown the power supply except specific part. - BACKUP RAM : 8KB - Port keep (Keep port status when BACKUP mode is set) - CEC Function Page 2 TMPM362F10FG ...
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... Clock gear function : The high-speed clock can be divided into 1/1, 1/2, 1/4 or 1/8. 21. Endian Little endian 22. Maximum operating frequency : 64MHz 23. Operating voltage range 2 3.6 V (with on-chip regulator) 24. Temperature range ・ -20 degrees to 85 degrees (except Flash writing / erasing) ・ 0 degrees to 70 degrees (during Flash writing / erasing) 25. Package LQFP144-P-2020-0.50E ( mm, 0.5 mm pitch) Page 3 TMPM362F10FG ...
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... ETM SWD FLASH (1MB) RAM (56KB) Backup RAM Cortex-M3 Controller NVIC AHB Lite Bus Matrix (8KB) SMC BOOT ROM AHB to APB Bridge Figure 1-1 TMPM362F10FG Block Diagram Page 4 TMPM362F10FG DMA CG PORT WDT RTC 16bit Timer SIO/UART (4byte FIFO) I2C/SIO 10bit ADC ...
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... Pin layout (Top view) Figure 1-2 shows the pin layout of TMPM362F10FG. PH3/INTC/TBBIN1 PH4/SDA4/SO4/TBDIN0 110 PH5/SCL4/SI4/TBDIN1 PH6/SCK4/TBEIN0 PH7/INTD/TBEIN1 RVDD3 XT1 115 XT2 DVDD3A X1 DVSS X2 120 DVDD3B DVSS PI2/INTE PI3/INTF NMI 125 TEST1 TEST2 PI0/BOOT Pl1/CEC AVDD3 130 PJ0/AIN0 PJ1/AIN1 PJ2/AIN2 PJ3/AIN3/ADTRG ...
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... Pin names and Functions 1.4 Pin names and Functions Table 1-1 sort input and output pins of TMPM362F10FG by pin or port. The table includes alternate pin names and function for multi-function pins. 1.4.1 Sorted by pin Table 1-1 Pin Names and Functions Sorted by Pin (1/10) ...
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... Receiving serial data I/O port Serial clock input / output Inputting the Timer B capture trigger Handshake input pin I/O port External interrupt pin Inputting the Timer B capture trigger Inputting signal to remote controller I/O port Sending serial data I/O port Receiving serial data Page 7 TMPM362F10FG ...
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... External interrupt pin Output Timer B output I/O I/O port Output Chip select pin I/O I/O port I/O I/O port Output Byte lane pin Output SSP data output pin I/O I/O port Output Byte lane pin Input SSP data input pin Page 8 TMPM362F10FG Function ...
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... I/O port data bus Address and data bus I/O port data bus Address and data bus I/O port data bus Address and data bus I/O port data bus Address and data bus I/O port data bus Address and data bus Page 9 TMPM362F10FG ...
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... Output Address bus Output Sending serial data I/O I/O port Output Address bus Input Receiving serial data I/O I/O port Output Address bus I/O Serial clock input / output Input Handshake input pin I/O I/O port Output Address bus Page 10 TMPM362F10FG Function ...
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... Address bus Inputting the Timer B capture trigger I/O port Address bus Inputting the Timer B capture trigger I/O port Address bus Inputting the Timer B capture trigger I/O port Address bus Sending serial data I/O port Address bus Receiving serial data Page 11 TMPM362F10FG ...
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... SIO mode : receive data pin Input Inputting the Timer B capture trigger I/O I/O port I/O Inputting and outputting a clock if the serial bus interface operates in the SIO mode. Output Chip select pin I/O I/O port Input External interrupt pin Output Chip select pin Page 12 TMPM362F10FG Function ...
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... If the serial bus interface operates - in the I2C mode : data pin - in the SIO mode : receive data pin Inputting the Timer B capture trigger I/O port Inputting and outputting a clock if the serial bus interface operates in the SIO mode. Inputting the Timer B capture trigger Page 13 TMPM362F10FG ...
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... Nch open drain port Supplying the AD converter with a power supply. - (note) AVDD3 must be connected to power supply even if A/D converter is not used. Input Input port Input Analog input Input Input port Input Analog input Input Input port Input Analog input Page 14 TMPM362F10FG Function ...
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... Key-on wake-up pin Input port Analog input Key-on wake-up pin Input port Analog input Key-on wake-up pin Input port Analog input Input port Analog input Input port Analog input Input port Analog input Input port Analog input Input port Analog input Page 15 TMPM362F10FG ...
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... Pin Numbers and Power Supply Pins 1.5 Pin Numbers and Power Supply Pins Table 1-2 PIn Numbers and Power Supplies Power supply DVDD3B DVDD3A AVDD3 RVDD3 Voltage range Pin No. PA,PB,PC,PD,PE,PF,PG,PH,PI,PL,PM 47,89,121 PN,PO,PP,XT1,XT2,RESET,NMI,MODE 117 2.7 to 3.6V 130 114 Page 16 TMPM362F10FG PIn mane X1,X2 PJ,PK − ...
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... ARM Limited. This chapter describes the functions unique to the TX03 series that are not explained in that docu- ment. 2.1 Information on the processor core The following table shows the revision of the processor core in the TMPM362F10FG. Refer to the detailed information about the CPU core and architecture, refer to the ARM manual "Cortex-M ser- ies processors" in the following URL : http://infocenter.arm.com/help/index.jsp 2 ...
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... SysTick The Cortex-M3 core has a SysTick timer which can generate SysTick exception. In the TMPM362F10FG, the clock that is input from X1 pin dividing used as a count clock for the Systic timer. SysTick calibration register can set a calibration value to measure 10ms. In this product, when 8MHz is input to X1 pin, calibration value is set to 0x9C4 which can measure 10ms. Additionally, if this value is read as " ...
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... The Cortex-M3 core has event output signals and event input signals. An event output signal is output by SEV in- struction execution event is input, the core returns from low-power consumption mode caused by WFE instruc- tion. TMPM362F10FG does not use event output signals and event input signals. Please do not use SEV instruction and WFE instruction. 2.5 ...
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... Exclusive access Page 20 TMPM362F10FG ...
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... Debug Interface 3.1 Specification Overview The TMPM362F10FG contains the Serial Wire Debug Port (SW-DP) unit for interfacing with the debugging tools and the Embedded Trace Macrocell ted pins (TRACEDATA[3:0]) via the on-chip Trace Port Interface Unit (TPIU). For details about SW-DP, ETM and TPIU, refer to "Cortex-M3 Technical Reference Manual". ...
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... TRACEDATA1 0 0 TRACEDATA2 0 0 TRACEDATA3 0 0 Page 22 TMPM362F10FG SW debug function Comments Serial Wire Data Input/Output (Always pull-up) Serial Wire Clock (Always pull-down) TRACE Clock Output TRACE DATA Output0 / Serial Wire Viewer Output TRACE DATA Output1 TRACE DATA Output2 TRACE DATA Output3 ...
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... Connection with a Debug Tool Concerning a connection with debug tools, refer to manufactures recommendations. Debug interface pins contain a pull-up resistor and a pull-down resistor.When debug interface pins are connec- ted with external pull-up or pull-down, please pay attention to input level. Page 23 TMPM362F10FG ...
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... Connection with a Debug Tool Page 24 TMPM362F10FG ...
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... Memory Map The memory maps for the TMPM362F10FG are based on the ARM Cortex-M3 processor core memory map. The internal ROM is mapped to the code of the Cortex-M3 core memory, the internal RAM is mapped to the SRAM region and the special function register (SFR) is mapped to the peripheral region respectively. ...
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... Memory Map 4.1.1 Memory map of the TMPM362F10FG Figure 4-1 shows the memory map of the TMPM362F10FG. Vender-Specific CPU Register Region Fault External Bus Area Fault SFR Fault SFR Fault SFR Fault SFR Fault Backup RAM (8K) Internal RAM (56K) Fault Internal ROM (1024K) ...
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... Reserved Port Timer B (16ch) I2C/SIO(5ch) SIO/UART(12ch) CEC RMC(2ch) 0x400F_001C to 0x400F_001F ADC(16ch) 0x400F_0024 to 0x400F_002F KWUP 0x400F_1010 to 0x400F_107F WDT RTC 0x400F_300D CG 0x400F_4036 to 0x4000_4FFF 0x41FF_F000 to 0x41FF_F007 0x41FF_F014 to 0x41FF_F017 FLASH 0x41FF_F018 to 0x41FF_F01B 0x41FF_F024 to 0x41FF_F02C 0x41FF_F033 to 0x41FF_F037 Reserved RAMWAIT Reserved Reserved SMCMOD Page 27 TMPM362F10FG ...
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... SFR area detail Page 28 TMPM362F10FG ...
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... Reset The TMPM362F10FG has three reset sources: an external reset pin (RESET), a watchdog timer (WDT) and the setting <SYSRESETREQ> in the Application Interrupt and Reset Control Register. For reset from the WDT, refer to the chapter on the WDT. For reset from <SYSRESETREQ>, refer to "Cortex-M3 Technical Reference Manual". ...
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... Cold reset Note 1: The power supply must be raised (from 0V to 2.7V speed of 0.1ms/V or slower. Note 2: Turn on the power while the RESET pin is fixed to "Low". When all the power supplies are stabilized within operating volt- age, release the reset. Page 30 TMPM362F10FG ...
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... As a precondition, ensure that the power supply voltage is within the operating range and the internal high- frequency oscillator is providing stable oscillation. To reset the TMPM362F10FG, assert the RESET signal (active low) for a minimum duration of 12 system clocks. After the external reset (RESET) signal is released, the internal reset signal remains asserted for a further 400μ ...
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... After reset Page 32 TMPM362F10FG ...
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... Controls the system clock ・ Controls the prescaler clock ・ Controls the PLL multiplication circuit ・ Controls the warm-up timer In addition to NORMAL mode, the TMPM362F10FG can operate in six types of low power mode to reduce pow- er consumption according to its usage conditions. Page 33 TMPM362F10FG ...
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... The following table shows the CG-related registers and addresses. System control register Oscillation control register Standby control register PLL selection register System clock selection register Register name CGSYSCR CGOSCCR CGSTBYCR CGPLLSEL CGCKSEL Page 34 TMPM362F10FG Base Address = 0x400F_4000 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 ...
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... Read as "0". 10- 8 PRCK[2:0] R/W Prescaler clock 000: fperiph 001: fperiph/2 010: fperiph/4 011: fperiph/8 100: fperiph/16 101: fperiph/32 110: Reserved 111: Reserved Specifies the prescaler clock to peripheral I/O. 7-3 − R Read as "0" FCSTOP - FPSEL1 FPSEL0 - Function Page 35 TMPM362F10FG SCOSEL PRCK GEAR ...
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... Registers Bit Bit Symbol Type 2-0 GEAR[2:0] R/W High-speed clock (fc) gear 000: fc 001: Reserved 010: Reserved 011: Reserved 100: fc/2 101: fc/4 110: fc/8 111: Reserved Page 36 TMPM362F10FG Function ...
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... It stops after reset.Setting the bit is required. 1 WUEF R Status of warm-up timer (WUP) 0: Warm-up completed. 1: Warm-up operation Enable to monitor the status of the warm-up timer. 0 WUEON W Operation of warm-up timer 0: don't care 1: Starting warm-up Enables to start the warm-up timer WUPT WUPSEL PLLON Function Page 37 TMPM362F10FG XTEN XEN WUEF WUEON ...
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... Low-speed oscillator operation after releasing the STOP mode. 0: Stop 1: Oscillation High-speed oscillator operation after releasing the STOP mode. 0: Stop 1: Oscillation Read as "0". Low power consumption mode 000: Reserved 001: STOP 010: SLEEP 011: IDLE2 100: Reserved 101: BACKUP STOP 110: BACKUP SLEEP 111: IDLE1 Page 38 TMPM362F10FG PTKEEP 0 ...
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... Others: Reserved 2-1 − R/W Write as "1". 0 PLLSEL R/W Use PLL 0: Disuse. X1 selected 1: Use Specifies use or disuse of the clock multiplied by the PLL. "X1" is automatically set after reset. Resetting is required when using the PLL Function Page 39 TMPM362F10FG C2S PLLSEL ...
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... Setting CGOSCCR<XEN> and <XTEN> to "1" in advance is required. System clock status 0: High-speed (fc) 1: Low-speed (fs) Shows the status of the system clock. Switching the oscillator with <SYSCK> generates time lag to complete. If the output of the oscillator specified in <SYSCK> is read out by <SYSCLKFLG>, the switching has been completed. Page 40 TMPM362F10FG ...
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... Reset operation causes all the clock configurations excluding the low-speed clock (fs the same as fosc fosc fsys = fosc φT0 = fosc For example, reset operation configures fsys as 10MHz when a 10MHz oscillator is connected to the pin. : fc, fc/2, fc/4, fc/8 : fs, fperiph, fperiph/2, fperiph/4, fperiph/8, fperiph/16, fperiph/32 : fsys : fosc/32 : oscillating : oscillating : stop : fc (no frequency dividing) Page 41 TMPM362F10FG ...
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... CGOSCCR<PLLON> Stops after releasing reset fs 1/32 CGSYSCR <FPSEL1> CGSYSCR 1/2 1/4 1/8 1/16 1/32 <PRCK[2:0]> 1/2 Figure 6-1 Clock Block Diagram Page 42 TMPM362F10FG ADC conversion FCSTOP clock <ADCLK> CGSYSCR<FPSEL0> fperiph ( I/O ) fgear fsys 1/8 CGSYSCR CGCKSEL <GEAR[2:0]> <SYSCK> fs Systick Timer input CPU(STCLK) φ ...
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... CGOSCCR <PLLON> = “0” (PLL stop) must be retained 100μs or more for stablization. By setting CGOSCCR<PLLON>=” 1”→“0” (PLL stop), multiplier factor will be initialized to “4” . Starting PLL operation needs to approximately 200μs or more stablization time by retaining CGOSCCR<PLLON>= “1” (PLL on). Page 43 TMPM362F10FG ...
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... It takes 100μs or more for the PLL to be stabilized when changed PLL setting to hole the CGOSCCR<PLLON>= “0” (PLL stop) It takes approx 200μs for the PLL to be stabilized. To hold the CGOSCCR<PLLON>=” 1” (PLL active). Figure 6-3 Changing the PLL setting Page 44 TMPM362F10FG Note ...
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... Check warm-up counter setting : Enable high-speed oscillation (fosc) : Enable warm-up counting (WUP) : Wait for "0" (end of WUP) : system clock changed to high-speed (fgear) : Wait for "0" (the current clock is fgear) : Disable the low-speed oscillation (fs) (In dual clock mode, it’s not required.) Page 45 TMPM362F10FG ...
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... Enable low-speed oscillation (fs) : Select XT1 for warm-up clock : Enable warm-up counting (WUP) : Wait for "0" (end of WUP) : system clock changed to low-speed (fs) : Wait for "1" (the current clock is fs) : Disable the high-speed oscillation (fc) (In dual clock mode, it’s not required.) Page 46 TMPM362F10FG ...
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... System Clock The TMPM362F10FG offers two selectable system clocks: low-speed or high-speed. The high-speed clock is dividable. Note 1: Switching of clock gear is executed when a value is written to the CGSYSCR<GEAR[2:0]> register. The ac- tual switching takes place after a slight delay. Note 2: When PLL is used as octuple, do not use the oscillator which is upper than 8MHz. ...
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... System Clock Pin Output Function TMPM362F10FG enables to output the system clock from a pin. The SCOUT pin can output the low speed clock fs, the system clock fsys and fsys/2, and the prescaler input clock for peripheral I/O φT0. The out- put clock is selected by setting the CGSYSCR<SCOSEL[1:0]>. ...
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... When the low-speed clock is not used, the SLOW and SLEEP modes cannot be used. Also, TMPM362F10FG has a BACKUP mode. This mode can reduce power consumption of full width by shutdown main power supply of almost function except particular one. ...
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... Note 1: Be sure to stop peripheral functions except for the CPU, TMRB, RTC, I/O ports, CEC, RMC and KWUP be- fore switching to the SLOW mode. Note 2: In the SLOW mode, be sure not to perform reset using the Application Interrupt and Reset Control Regis- ter <SYSRESETREQ> of the Cortex-M3 NVIC register. Page 50 TMPM362F10FG ...
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... Releasing by the interrupt requires settings in advance. See the chapter "Exceptions" for details. Note 1: The TMPM362F10FG does not offer any event for releasing the low power consumption mode. Transition to the low power consumption mode by executing the WFE (Wait For Event) instruction is prohibited. ...
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... Pin name I/O Input only Output only Input only Input Output Input Output Input Output Input Output Input Output Page 52 TMPM362F10FG <DRVE> <DRVE> × × "High" level output "High" level output ο ο ο ο × Depends on (PxCR[m]) ο ο × ...
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... Table 6-6 shows the mode setting in the <STBY[2:0]>. Table 6-6 Low power consumption mode setting BACKUP SLEEP Note:Do not use reserved mode setting. CGSTBYCR Mode <STBY[2:0]> Reserved 000 STOP 001 SLEEP 010 IDLE2 011 Reserved 100 BACKUP STOP 101 110 IDLE1 111 Page 53 TMPM362F10FG ...
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... Page 54 TMPM362F10FG BACKUP SLEEP STOP SLEEP − − × − − × ο ο × − − × ο (note 6) ο (note 2) Δ (note 3) Δ ...
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... Releasing the Low Power Consumption Mode The low power consumption mode can be released by an interrupt request, Non-Maskable Interrupt (NMI) or reset. The release source that can be used is determined by the low power consumption mode selected. Details are shown in Table 6-8. Page 55 TMPM362F10FG ...
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... Page 56 TMPM362F10FG BACKUP BACKUP SLEEP STOP (note 2) (note 2) ο ο × × ο × × × × × × × × × ...
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... Auto-warm-up (note 3) High-speed oscillator : more than 100μs Auto-warm-up High-speed oscillator : Setting value of warm-up time Not required Auto-warm-up High-speed oscillator : Setting value of warm-up time Auto-warm-up Low-speed oscillator :Setting value of warm-up time Auto-warm-up (note 3) High-speed oscillator : more than 500μs Page 57 TMPM362F10FG ...
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... Table 6-9 Warm-up setting in mode transition Mode transition Warm-up setting Auto-warm-up (note 3) BACKUP STOP → NORMAL High-speed oscillator : more than Auto-warm-up (note 3) BACKUP SLEEP → SLOW Low-speed oscillator : more than Auto-warm-up (note 3) BACKUP STOP → SLOW Low-speed oscillator : more than Page 58 TMPM362F10FG 500μs 2.5ms 2.5ms ...
Page 83
... System clock stops Release event occurs STOP High-speed clock starts oscillating Warm-up completes. Warm-up starts System clock starts. Release event occurs SLEEP Oscillation continues High-speed clock starts oscillating Warm-up completes. Warm-up starts System clock starts. Page 59 TMPM362F10FG NORMAL NORMAL ...
Page 84
... WFI excute/ sleep on exit Release event occurs STOP System clock stops Low-speed clock starts oscillating Warm-up starts WFI excute/ sleep on exit SLEEP System clock stops Page 60 TMPM362F10FG SLOW Warm-up completes System clock starts Release event occurs SLOW System clock starts ...
Page 85
... For detailed descriptions on each exception, refer to "Cortex-M3 Technical Reference Manual". ・ Reset ・ Non-Maskable Interrupt (NMI) ・ Hard Fault ・ Memory Management ・ Bus Fault ・ Usage Fault ・ SVCall (Supervisor Call) ・ Debug Monitor ・ PendSV ・ SysTick ・ External Interrupt Page 61 TMPM362F10FG ...
Page 86
... The CG/CPU detects the exception request. The CPU handles the exception request. The CPU branches to the corresponding interrupt service routine (ISR). Necessary processing is executed. The CPU branches to another ISR or returns to the previous program. Page 62 TMPM362F10FG See Section 7.1.2.1 Section 7.1.2.2 Section 7.1.2.4 Section 7.1.2.4 ...
Page 87
... Access violation to the Hard Fault region of the memory map Undefined instruction execution or other faults related to instruction ex- ecution System service call with SVC instruction Debug monitor when the CPU is not faulting Pendable system service request Notification from system timer External interrupt pin or peripheral function (Note2) Page 63 TMPM362F10FG ...
Page 88
... Pre-emption Subpriority field field [7:1] [0] [7:2] [1:0] [7:3] [2:0] [7:4] [3:0] [7:5] [4:0] [7:6] [5:0] [7] [6:0] None [7:0] ple, in the case of 3-bit configuration, the priority is set as <PRI_n[7:5]> and <PRI_n[4:0] > is "00000". Page 64 TMPM362F10FG Number of Number of pre-emption subpriorities priorities 128 128 1 256 ...
Page 89
... A late-arriving exception causes the CPU to fetch a new vector address for branching to the corre- sponding ISR, but the CPU does not newly push the register contents to the stack. (4) Vector table The vector table is configured as shown below. Old SP → <previous> xPSR PC LR r12 → r0 Page 65 TMPM362F10FG ...
Page 90
... Bus Fault ISR address Usage Fault ISR address Reserved SVCall ISR address Debug Monitor ISR address Reserved PendSV ISR address SysTick ISR address External Interrupt ISR address Page 66 TMPM362F10FG Setting Required Required Required Required Optional Optional Optional Optional Optional Optional Optional Optional ...
Page 91
... Load current active interrupt number Loads the current active interrupt number from the stacked xPSR. The CPU uses this to track which interrupt to return to. ・ Select SP If returning to an exception (Handler Mode SP_main. If returning to Thread Mode, SP can be SP_main or SP_process. Page 67 TMPM362F10FG ...
Page 92
... Note:In this product, the system timer counts based on a clock obtained by dividing the clock input from the X1 pin by 32.The SysTick Calibration Value Register is set to 0x9C4, which provides 10 ms tim- ing when the clock input from MHz. Page 68 TMPM362F10FG ...
Page 93
... Port interrupt pin Peripheral function 7.5.1.2 Generation An interrupt request is generated from an external pin or peripheral function assigned as an interrupt source or by setting the NVIC's Interrupt Set-Pending Register. Interrupt request <INTxEN> Exiting standby mode Clock generator Figure 7-1 Interrupt Route Page 69 TMPM362F10FG CPU ...
Page 94
... Set the port control register so that the external pin can perform as an interrupt function pin. Set the peripheral function to make it possible to output interrupt requests. See the chapter of each peripheral function for details. An interrupt request can be generated by setting the relevant bit of the Interrupt Set-Pend- Page 70 TMPM362F10FG ...
Page 95
... AD conversion monitoring function interrupt 1 40 INTTB0 16-bit TMRB match detection 0 41 INTTB1 16-bit TMRB match detection 1 42 INTTB2 16-bit TMRB match detection 2 active level (Clearing standby) Selectable Rising edge Falling edge High level Page 71 TMPM362F10FG CG interrupt mode control register CGIMCGA CGIMCGB CGIMCGC CGIMCGD CGIMCGE CGIMCGF ...
Page 96
... TMRB input capture 51 16-bit TMRB input capture 60 16-bit TMRB input capture 61 16-bit TMRB input capture 70 16-bit TMRB input capture 71 16-bit TMRB input capture 90 16-bit TMRB input capture 91 16-bit TMRB input capture A0 Page 72 TMPM362F10FG active level CG interrupt mode (Clearing standby) control register ...
Page 97
... Note:For the CEC reception / transmission, remote control signal reception and real time clock in- terrupts, set the <INTxEN> bit to "1" and specify the active level, even when they are not used for clearing a standby mode. active level (Clearing standby) Page 73 TMPM362F10FG CG interrupt mode control register ...
Page 98
... If multiple interrupt requests occur simultaneously, the interrupt request with the highest priority is detected according to the priority order. The CPU handles the interrupt. The CPU pushes register contents to the stack before entering the ISR. Page 74 TMPM362F10FG See "7.5.2.2 Preparation" "7.5.2.3 Detection by Clock Generator" ...
Page 99
... Processing Program for the ISR. ISR execution Clear the interrupt source if needed. Return to preceding Configure to return to the preceding program of the ISR. program Details Page 75 TMPM362F10FG See "7.5.2.6 Interrupt Serv- ice Routine (ISR)" ...
Page 100
... Each interrupt source is provided with eight bits for assigning a priority level from 0 to 255, but the number of bits actually used varies with each product.Priority level 0 is the highest priority lev- el.If multiple sources have the same priority, the smallest-numbered interrupt source has the highest priority. ← "1"(Interrupt disabled) Page 76 TMPM362F10FG ...
Page 101
... Before enabling an interrupt, clear the corresponding interrupt request already held. This can avoid unexpected interrupt.To clear corresponding interrupt request, write a value corresponding to the interrupt to be used to the CGICRCG register.See "7.6.3.7 CGICRCG (CG Interrupt Request Clear Register)" for each value. Page 77 TMPM362F10FG ...
Page 102
... If a standby mode is exited without clearing the interrupt request, the same interrupt will be detected again when normal operation is resumed. Be sure to clear each interrupt request in the ISR. ← active level ← Value corresponding to the interrupt to be used ← "1" (interrupt enabled) ← "1" ← "1" ← "0" Page 78 TMPM362F10FG ...
Page 103
... Therefore, the interrupt source must be cleared. Clearing the interrupt source au- tomatically clears the interrupt request signal from the clock generator interrupt is set as edge-sensitive, clear an interrupt request by setting the corresponding val the CGICRCG register. When an active edge occurs again, a new interrupt request will be detec- ted. Page 79 TMPM362F10FG ...
Page 104
... Reserved Reserved Note:Access to the "Reserved" areas is prohibited. Register name Register name CGICRCG CGNMIFLG CGRSTFLG CGIMCGA CGIMCGB CGIMCGC CGIMCGD CGIMCGE CGIMCGF - - Page 80 TMPM362F10FG Base Address = 0xE000_E000 Address 0x0010 0x0014 0x0018 0x001C 0x0100 0x0104 0x0108 0x010C 0x0180 0x0184 0x0188 0x018C 0x0200 0x0204 0x0208 ...
Page 105
... Clears on read of any part of the SysTick Control and Status Register. 15-3 − R Read CLKSOURCE R/W 0: External reference clock 1: CPU clock 1 TICKINT R not pend SysTick 1: Pend SysTick 0 ENABLE R/W 0: Disable 1: Enable If "1" is set, it reloads with the value of the Reload Value Register and starts operation CLKSOURCE Function Page 81 TMPM362F10FG COUNTFLAG TICKINT ENABLE ...
Page 106
... Set the value to load into the SysTick Current Value Register when the timer reaches "0" CURRENT Undefined CURRENT Undefined CURRENT Undefined Read as 0. [Read] Current SysTick timer value [Write] Clear Writing to this register with any value clears Clearing this register also clears the <COUNTFLAG> bit of the SysTick Control and Status Register. Page 82 TMPM362F10FG Function ...
Page 107
... Note:In this product, the system timer counts based on a clock obtained by dividing the clock input from the X1 pin by 32.The SysTick Calibration Value Register is set to a value that provides 10 ms timing when the cock input from MHz TENMS TENMS TENMS Function Page 83 TMPM362F10FG ...
Page 108
... Disabled 1: Enabled Each bit corresponds to the specified number of interrupts. Writing "1" bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Page 84 TMPM362F10FG SETENA SETENA SETENA (Interrupt 27) ...
Page 109
... SETENA (Interrupt 60) (Interrupt 59) (Interrupt 58 SETENA SETENA SETENA (Interrupt 52) (Interrupt 51) (Interrupt 50 SETENA SETENA SETENA (Interrupt 44) (Interrupt 43) (Interrupt 42 SETENA SETENA SETENA (Interrupt 36) (Interrupt 35) (Interrupt 34 Function Page 85 TMPM362F10FG SETENA - - SETENA SETENA SETENA (Interrupt 49) (Interrupt 48 SETENA SETENA SETENA (Interrupt 41) (Interrupt 40 SETENA SETENA SETENA (Interrupt 33) (Interrupt 32 ...
Page 110
... Disabled 1: Enabled Each bit corresponds to the specified number of interrupts. Writing "1" bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Page 86 TMPM362F10FG SETENA SETENA SETENA (Interrupt 91) ...
Page 111
... Writing "1" bit in this register enables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources" SETENA SETENA - - (Interrupt 99) (Interrupt 98 Function Page 87 TMPM362F10FG SETENA SETENA (Interrupt 97) (Interrupt 96 ...
Page 112
... Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Page 88 TMPM362F10FG CLRENA ...
Page 113
... CLRENA (Interrupt 60) (Interrupt 59) (Interrupt 58 CLRENA CLRENA CLRENA (Interrupt 52) (Interrupt 51) (Interrupt 50 CLRENA CLRENA CLRENA (Interrupt 44) (Interrupt 43) (Interrupt 42 CLRENA CLRENA CLRENA (Interrupt 36) (Interrupt 35) (Interrupt 34 Function Page 89 TMPM362F10FG CLRENA - - CLRENA CLRENA CLRENA (Interrupt 49) (Interrupt 48 CLRENA CLRENA CLRENA (Interrupt 41) (Interrupt 40 CLRENA CLRENA CLRENA (Interrupt 33) (Interrupt 32 ...
Page 114
... Each bit corresponds to the specified number of interrupts. It can be performed to enable interrupts and to check if interrupts are disabled. Writing "1" bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Page 90 TMPM362F10FG CLRENA ...
Page 115
... Writing "1" bit in this register disables the corresponding interrupt. Writing "0" has no effect. Reading the bits can see the enable/disable condition of the corresponding interrupts. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources" CLRENA CLRENA - - (Interrupt 99) (Interrupt 98 Function Page 91 TMPM362F10FG CLRENA CLRENA (Interrupt 97) (Interrupt 96 ...
Page 116
... Writing "1" bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Writing "1" corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. Page 92 TMPM362F10FG SETPEND ...
Page 117
... Undefined Undefined Undefined SETPEND SETPEND (Interrupt 44) (Interrupt 43) (Interrupt 42) Undefined Undefined Undefined SETPEND SETPEND (Interrupt 36) (Interrupt 35) (Interrupt 34) Undefined Undefined Undefined Function Page 93 TMPM362F10FG SETPEND - - Undefined Undefined Undefined SETPEND SETPEND SETPEND (Interrupt 49) (Interrupt 48) Undefined Undefined Undefined SETPEND SETPEND SETPEND (Interrupt 41) (Interrupt 40) ...
Page 118
... Writing "1" bit in this register pends the corresponding interrupt. However, writing "1" has no effect on an interrupt that is already pending or is disabled. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Writing "1" corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. Page 94 TMPM362F10FG SETPEND ...
Page 119
... Reading the bit returns the current state of the corresponding interrupts. Writing "1" corresponding bit in the Interrupt Clear-Pending Register clears the bit in this register. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources" SETPEND SETPEND - - (Interrupt 99) (Interrupt 98 Undefined Undefined Function Page 95 TMPM362F10FG SETPEND SETPEND (Interrupt 97) (Interrupt 96) Undefined Undefined ...
Page 120
... Writing "1" bit in this register clears the corresponding pending interrupt. However, writing "1" has no ef- fect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Page 96 TMPM362F10FG CLRPEND ...
Page 121
... Undefined Undefined Undefined CLRPEND CLRPEND CLRPEND (Interrupt 44) (Interrupt 43) (Interrupt 42) Undefined Undefined Undefined CLRPEND CLRPEND CLRPEND (Interrupt 36) (Interrupt 35) (Interrupt 34) Undefined Undefined Undefined Function Page 97 TMPM362F10FG Undefined Undefined Undefined CLRPEND CLRPEND (Interrupt 49) (Interrupt 48) Undefined Undefined Undefined CLRPEND CLRPEND (Interrupt 41) (Interrupt 40) Undefined Undefined Undefined ...
Page 122
... Writing "1" bit in this register clears the corresponding pending interrupt. However, writing "1" has no ef- fect on an interrupt that is already being serviced. Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Page 98 TMPM362F10FG CLRPEND ...
Page 123
... Writing "0" has no effect. Reading the bit returns the current state of the corresponding interrupts. Note:For descriptions of interrupts and interrupt numbers, see Section "7.5.1.5 List of Interrupt Sources" CLRPEND CLRPEND - - (Interrupt 99) (Interrupt 98 Undefined Undefined Function Page 99 TMPM362F10FG CLRPEND CLRPEND (Interrupt 97) (Interrupt 96) Undefined Undefined ...
Page 124
... PRI_63 PRI_62 PRI_67 PRI_66 PRI_71 PRI_70 PRI_75 PRI_74 − − PRI_83 PRI_82 PRI_87 PRI_86 PRI_91 PRI_90 PRI_95 PRI_94 PRI_99 PRI_98 Page 100 TMPM362F10FG PRI_1 PRI_0 PRI_5 PRI_4 PRI_9 PRI_8 PRI_13 PRI_12 PRI_17 PRI_16 PRI_21 PRI_20 PRI_25 PRI_24 PRI_29 PRI_28 PRI_33 PRI_32 ...
Page 125
... R/W Priority of interrupt number 1 12-8 − R Read as 0, 7-5 PRI_0 R/W Priority of interrupt number 0 4-0 − R Read − − − − − − − − Function Page 101 TMPM362F10FG − − − − − − − − − − − − ...
Page 126
... The offset must be aligned based on the number of exceptions in the table.This means that the minimum alignment is 32 words that you can use for interrupts.For more interrupts, you must adjust the align- ment by rounding up to the next power of two. Read as 0, Page 102 TMPM362F10FG TBLOFF ...
Page 127
... Resets the system, with the exception of debug components (FPB, DWT and ITM) by setting "1" and this bit is also zero cleared. Note 1: Little-endian is the default memory format for this product. Note 2: When SYSRESETREQ is output, warm reset is performed on this product. <SYSRESETREQ> is cleared by warm reset VECTKEY/VECTKEYSTAT VECTKEY/VECTKEYSTAT SYSRESET - - - REQ Function Page 103 TMPM362F10FG PRIGROUP VECTCLR VECTRESET ACTIVE ...
Page 128
... PRI_15 PRI_14 (SysTick) (PendSV PRI_7 - PRI_6 - PRI_5 - PRI_4 - Reserved Read as 0, Priority of Usage Fault Read as 0, Priority of Bus Fault Read as 0, Priority of Memory Management Read as 0, Page 104 TMPM362F10FG PRI_5 PRI_4 (Bus Fault) (Memory Management) PRI_9 PRI_8 PRI_13 PRI_12 (Debug Monitor ...
Page 129
... Inactive 1: Active 9 − R Read MONITORACT R/W Debug monitor 0: Inactive 1: Active 7 SVCALLACT R/W SVCall 0: Inactive 1: Active 6-4 − R Read USGFAULT - - - USGFAULT SYSTICKACT PENDSVACT PENDED PENDED USGFAULT - - ACT Function Page 105 TMPM362F10FG BUSFAULT MEMFAULT ENA ENA ENA MONITOR - ACT BUSFAULT MEMFAULT - ACT ACT ...
Page 130
... R/W ACT Note:You must clear or set the active bits with extreme caution because clearing and setting these bits does not re- pair stack contents. Usage Fault 0: Inactive 1: Active Read as 0, Bus Fault 0: Inactive 1: Active Memory management 0: Inactive 1: Active Page 106 TMPM362F10FG Function ...
Page 131
... INT2 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge 17 − R Reads as undefined. 16 INT2EN R/W INT2 clear input 0:Disable 1: Enable 15 − R Read EMCG3 EMST3 EMCG2 EMST2 EMCG1 EMST1 EMCG0 EMST0 Function Page 107 TMPM362F10FG INT3EN 0 Undefined INT2EN 0 Undefined INT1EN 0 Undefined INT0EN 0 Undefined 0 ...
Page 132
... INT0 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge active level of INT0 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge Reads as undefined. INT0 clear input 0: Disable 1: Enable Page 108 TMPM362F10FG Function ...
Page 133
... INT5 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge EMCG7 EMST7 EMCG6 EMST6 EMCG5 EMST5 EMCG4 EMST4 Function Page 109 TMPM362F10FG INT7EN 0 Undefined INT6EN 0 Undefined INT5EN 0 Undefined INT4EN 0 Undefined 0 ...
Page 134
... INT4 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge active level of INT4 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge Reads as undefined. INT4 clear input 0: Disable 1: Enable Page 110 TMPM362F10FG Function ...
Page 135
... INT9 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge EMCGB EMSTB EMCGA EMSTA EMCG9 EMST9 EMCG8 EMST8 Function Page 111 TMPM362F10FG INTBEN 0 Undefined INTAEN 0 Undefined INT9EN 0 Undefined INT8EN 0 Undefined 0 ...
Page 136
... INT8 standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge active level of INT8 standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge Reads as undefined. INT8 clear input 0: Disable 1: Enable Page 112 TMPM362F10FG Function ...
Page 137
... INTD standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge EMCGF EMSTF EMCGE EMSTE EMCGD EMSTD EMCGC EMSTC Function Page 113 TMPM362F10FG INTFEN 0 Undefined INTEEN 0 Undefined INTDEN 0 Undefined INTCEN 0 Undefined 0 ...
Page 138
... INTC standby clear request. (101 to 111: setting prohibited) 000: "Low" level 001: "High" level 010: Falling edge 011: Rising edge 100: Both edge active level of INTC standby clear request 00: − 01: Rising edge 10: Falling edge 11: Both edge Reads as undefined. INTC clear input 0: Disable 1: Enable Page 114 TMPM362F10FG Function ...
Page 139
... INTCECTX standby clear request. 00: − 01: Rising edge 10: Falling edge 11: Both edge 9 − R Read as undefined 8 INTHEN R/W INTCECTX Clear input 0:Disable 1: Enable EMCGJ EMSTJ EMCGI EMSTI EMCGH EMSTH EMCGG EMSTG Function Page 115 TMPM362F10FG INTJEN 0 Undefined INTIEN 0 Undefined INTHEN 0 Undefined INTGEN 0 Undefined 0 ...
Page 140
... Read as 0, active level setting of INTCECRX standby clear request. Set it as shown below. 011: Rising edge active level of INTCECRX standby clear request. 00: − 01: Rising edge 10: Falling edge 11: Both edge Read as undefined. INTCECRX Clear input 0:Disable 1: Enable Page 116 TMPM362F10FG Function ...
Page 141
... If interrupts are cleared with the CGICRCG register, <EMSTx> is also cleared. Note 2: Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is pro- hibited EMCGL EMSTL EMCGK EMSTK Function Page 117 TMPM362F10FG INTLEN 0 Undefined INTKEN 0 Undefined 0 ...
Page 142
... Read as 0, Clear interrupt requests. 0_0000:INT0 0_1000: INT8 0_0001: INT1 0_1001: INT9 0_0010: INT2 0_1010: INTA 0_0011: INT3 0_1011: INTB 0_0100: INT4 0_1100: INTC 0_0101: INT5 0_1101: INTD 0_0110: INT6 0_1110: INTE 0_ 0111: INT7 0_1111: INTF Read as 0. Page 118 TMPM362F10FG ...
Page 143
... Bit Symbol Type 31-2 − R Read NMIFLG1 R NMI source generation flag 0: not applicable 1:generated from NMI pin. 0 NMIFLG0 R NMI source generation flag 0: not applicable 1: generated from WDT Note:<NMIFLG> are cleared to "0" when they are read Function Page 119 TMPM362F10FG NMIFLG1 NMIFLG0 ...
Page 144
... Reset from SYSRESETREQ BACKUP reset flag 0: "0" is written 1: Reset from BACKUP mode release WDT reset flag 0: "0" is written 1: Reset from WDT RESET pin flag 0: "0" is written 1: Reset from RESET pin Power-on flag 0: "0" is written 1: Reset from power-on reset Page 120 TMPM362F10FG ...
Page 145
... Input / Output Ports 8.1 Port Functions 8.1.1 Function list TMPM362F10FG has 120 ports. Besides the ports function, these ports can be used as I/O pins for peripher- al functions. Table 8-1 shows the port function table. Table 8-1 Port Function List Input / Port PIn ...
Page 146
... Pull-up I/O ο ο (Note2) Input Pull-up ο − Input Pull-up ο − Page 122 TMPM362F10FG Program- mable Function pin Open-drain ο A14 , RXD11 ο A15 , SCLK11 , CTS11 ο A16 , INTB ο A17 , TB5IN0 ο A18 , TB5IN1 ο A19 , TB6IN0 ο ...
Page 147
... SCLK4 , TB2IN0 , CTS4 ο ο ο INT4 , TB2IN1 , RMC0 ο − ο TXD5 ο − ο RXD5 ο − ο SCLK5 , TBFIN0 , CTS5 ο ο ο INT8 , TBFIN1 , RMC1 ο − ο TXD6 , TB8OUT ο − ο RXD6 , TB9OUT Page 123 TMPM362F10FG ...
Page 148
... Pull-up − − I/O Pull-up − − I/O Pull-up − − I/O Pull-up ο − Page 124 TMPM362F10FG Program- mable Function pin Open-drain ο SCLK6 , TBAOUT , CTS6 ο INT9 , TBBOUT ο TXD7 , TBCOUT ο RXD7 , TBDOUT ο SCLK7 , TBEOUT , CTS7 ο ...
Page 149
... When PxOD is set "1",output buffer is disabled and pseudo-open-drain is materialized. ・ PxPUP: Port x pull-up control register To control programmable pull ups. ・ PxPDN: Port x pull-down control register To control programmable pull downs. ・ PxIE : Port x input control register To control inputs. For avoided through current, default setting prohibits inputs. Page 125 TMPM362F10FG ...
Page 150
... Pin name I/O Input only Output only Input only Input Output Input Output Input Output Input Output Input Output Page 126 TMPM362F10FG <DRVE> <DRVE> × × "High" Level Output "High"Level Output ο ο ο ο × Depend on PxCR[m] ο ο × ...
Page 151
... Port A output control register Port A function register 1 Port A open drain control register Port A pull-up control register Port A input control register Register name PADATA PACR PAFR1 PAOD PAPUP PAIE Page 127 TMPM362F10FG Base Address = 0x400C_0000 Address (Base+) 0x0000 0x0004 0x0008 0x0028 0x002C 0x0038 ...
Page 152
... PA7C After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PA7C to PA0C R PA6 PA5 PA4 Read as 0. Port A data register PA6C PA5C PA4C Read as 0. Output 0: Disable 1: Enable Page 128 TMPM362F10FG PA3 PA2 PA1 Function PA3C PA2C PA1C Function PA0 ...
Page 153
... D6, AD6 5 PA5F1 R/W 0: PORT 1: D5, AD5 4 PA4F1 R/W 0: PORT 1: D4, AD4 3 PA3F1 R/W 0: PORT 1: D3, AD3 2 PA2F1 R/W 0: PORT 1: D2, AD2 1 PA1F1 R/W 0: PORT 1: D1, AD1 0 PA0F1 R/W 0: PORT 1: D0, AD0 PA5F1 PA4F1 PA3F1 Function Page 129 TMPM362F10FG PA2F1 PA1F1 PA0F1 ...
Page 154
... PA7UP After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PA7UP to R/W PA0UP PA6OD PA5OD PA4OD Read CMOS 1 : Open-drain PA6UP PA5UP PA4UP Read as 0. Pull-Up 0: Disable 1: Enable Page 130 TMPM362F10FG PA3OD PA2OD PA1OD Function PA3UP PA2UP PA1UP Function PA0OD ...
Page 155
... After reset bit symbol - - After reset bit symbol PA7IE PA6IE After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PA7IE to PA0IE R/W Input 0: Disable 1: Enable PA5IE PA4IE PA3IE Function Page 131 TMPM362F10FG PA2IE PA1IE PA0IE ...
Page 156
... Port B output control register Port B function register 1 Port B open drain control register Port B pull-up control register Port B input control register Register name PBDATA PBCR PBFR1 PBOD PBPUP PBIE Page 132 TMPM362F10FG Base Address = 0x400C_0100 Address (Base+) 0x0000 0x0004 0x0008 0x0028 0x002C 0x0038 0 T1 ...
Page 157
... After reset bit symbol PB7C PB6C After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PB7C to PB0C R/W Output 0: Disable 1: Enable PB5 PB4 PB3 Function PB5C PB4C PB3C Function Page 133 TMPM362F10FG PB2 PB1 PB0 PB2C PB1C PB0C ...
Page 158
... PB2F1 R/W 1 PB1F1 R/W 0 PB0F1 R PB6F1 PB5F1 PB4F1 Read PORT 1 : D15, AD15 0: PORT 1: D14, AD14 0: PORT 1: D13, AD13 0: PORT 1: D12, AD12 0: PORT 1: D11, AD11 0: PORT 1: D10, AD10 0: PORT 1: D9, AD9 0: PORT 1: D8, AD8 Page 134 TMPM362F10FG PB3F1 PB2F1 PB1F1 Function PB0F1 0 ...
Page 159
... After reset bit symbol PB7UP PB6UP After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PB7UP to R/W Pull-up PB0UP 0: Disable 1: Enable PB5OD PB4OD PB3OD Function PB5UP PB4UP PB3UP Function Page 135 TMPM362F10FG PB2OD PB1OD PB0OD PB2UP PB1UP PB0UP ...
Page 160
... After reset 0 15 bit symbol - After reset 0 7 bit symbol PB7IE After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PB7IE to PB0IE R PB6IE PB5IE PB4IE Read as 0. Input 0: Disable 1: Enable Page 136 TMPM362F10FG PB3IE PB2IE PB1IE Function PB0IE 0 ...
Page 161
... Port C function register 2 Port C function register 3 Port C open drain control register Port C pull-up control register Port C input control register Base Address = 0x400C_0200 PCDATA PCCR PCFR1 PCFR2 PCFR3 PCOD PCPUP PCIE Page 137 TMPM362F10FG Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0028 0x002C 0x0038 ...
Page 162
... PC7C After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PC7C to PC0C R PC6 PC5 PC4 Read as 0. Port C data register PC6C PC5C PC4C Read as 0. Output 0: Disable 1: Enable Page 138 TMPM362F10FG PC3 PC2 PC1 Function PC3C PC2C PC1C Function PC0 ...
Page 163
... Bit Bit Symbol Type 31-8 − R Read PC7F1 R PORT PC6F1 R/W 0: PORT 1:A7 5 PC5F1 R/W 0: PORT PC4F1 R/W 0: PORT PC3F1 R/W 0: PORT PC2F1 R/W 0: PORT PC1F1 R/W 0: PORT PC0F1 R/W 0: PORT PC5F1 PC4F1 PC3F1 Function Page 139 TMPM362F10FG PC2F1 PC1F1 PC0F1 ...
Page 164
... Bit Symbol Type 31-7 − PC6F2 R/W 5 PC5F2 R/W 4 PC4F2 R/W 3 − PC2F2 R/W 1 PC1F2 R/W 0 PC0F2 R PC6F2 PC5F2 PC4F2 Read PORT 1:SCLK9 0: PORT 1: RXD9 0: PORT 1: TXD9 Read PORT 1: SCLK8 0: PORT 1: RXD8 0: PORT 1: TXD8 Page 140 TMPM362F10FG PC2F2 PC1F2 Function PC0F2 0 ...
Page 165
... After reset bit symbol - - After reset bit symbol PC7OD PC6OD After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PC7OD to R CMOS PC0OD 1 : Open-drain Function PC5OD PC4OD PC3OD Function Page 141 TMPM362F10FG PC2F3 - - PC2OD PC1OD PC0OD ...
Page 166
... PC7IE After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PC7IE to R/W PC0IE PC6UP PC5UP PC4UP Read as 0. Pull-up 0: Disable 1: Enable PC6IE PC5IE PC4IE Read as 0. Input 0: Disable 1: Enable Page 142 TMPM362F10FG PC3UP PC2UP PC1UP Function PC3IE PC2IE PC1IE Function PC0UP ...
Page 167
... Port D function register 2 Port D function register 3 Port D open drain control register Port D pull-up control register Port D input control register Base Address = 0x400C_0300 PDDATA PDCR PDFR1 PDFR2 PDFR3 PDOD PDPUP PDIE Page 143 TMPM362F10FG Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0028 0x002C 0x0038 ...
Page 168
... PD7C After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PD7C to PD0C R PD6 PD5 PD4 Read as 0. Port D data register PD6C PD5C PD4C Read as 0. Output 0: Disable 1: Enable Page 144 TMPM362F10FG PD3 PD2 PD1 Function PD3C PD2C PD1C Function PD0 ...
Page 169
... Read PD7F1 R PORT 1 : A16 6 PD6F1 R/W 0: PORT 1:A15 5 PD5F1 R/W 0: PORT 1: A14 4 PD4F1 R/W 0: PORT 1: A13 3 PD3F1 R/W 0: PORT 1: A12 2 PD2F1 R/W 0: PORT 1: A11 1 PD1F1 R/W 0: PORT 1: A10 0 PD0F1 R/W 0: PORT PD5F1 PD4F1 PD3F1 Function Page 145 TMPM362F10FG PD2F1 PD1F1 PD0F1 ...
Page 170
... R 7 PD7F2 R/W 6 PD6F2 R/W 5 PD5F2 R/W 4 PD4F2 R/W 3 − PD2F2 R/W 1 PD1F2 R/W 0 PD0F2 R PD6F2 PD5F2 PD4F2 Read PORT 1 : INTB 0: PORT 1:SCLK11 0: PORT 1: RXD11 0: PORT 1: TXD11 Read PORT 1: SCLK10 0: PORT 1: RXD10 0: PORT 1: TXD10 Page 146 TMPM362F10FG PD2F2 PD1F2 Function PD0F2 0 ...
Page 171
... After reset bit symbol - - After reset bit symbol PD7OD PD6OD After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PD7OD to R CMOS PD0OD 1 : Open-drain Function PD5OD PD4OD PD3OD Function Page 147 TMPM362F10FG PD2F3 - - PD2OD PD1OD PD0OD ...
Page 172
... PD7IE After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PD7IE to R/W PD0IE PD6UP PD5UP PD4UP Read as 0. Pull-up 0: Disable 1: Enable PD6IE PD5IE PD4IE Read as 0. Input 0: Disable 1: Enable Page 148 TMPM362F10FG PD3UP PD2UP PD1UP Function PD3IE PD2IE PD1IE Function PD0UP ...
Page 173
... Port E function register 2 Port E function register 3 Port E open drain control register Port E pull-up control register Port E input control register Base Address = 0x400C_0400 PEDATA PECR PEFR1 PEFR2 PEFR3 PEOD PEPUP PEIE Page 149 TMPM362F10FG Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0028 0x002C 0x0038 ...
Page 174
... PE7C After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PE7C to PE0C R PE6 PE5 PE4 Read as 0. Port E data register PE6C PE5C PE4C Read as 0. Output 0: Disable 1: Enable Page 150 TMPM362F10FG PE3 PE2 PE1 Function PE3C PE2C PE1C Function PE0 ...
Page 175
... R/W Write "0". 6 PE6F1 R/W 0: PORT 1:A23 5 PE5F1 R/W 0: PORT 1: A22 4 PE4F1 R/W 0: PORT 1: A21 3 PE3F1 R/W 0: PORT 1: A20 2 PE2F1 R/W 0: PORT 1: A19 1 PE1F1 R/W 0: PORT 1: A18 0 PE0F1 R/W 0: PORT 1: A17 PE5F1 PE4F1 PE3F1 Function Page 151 TMPM362F10FG PE2F1 PE1F1 PE0F1 ...
Page 176
... PE6F2 R/W 5 PE5F2 R/W 4 PE4F2 R/W 3 PE3F2 R/W 2 PE2F2 R/W 1 PE1F2 R/W 0 PE0F2 R PE6F2 PE5F2 PE4F2 Read PORT 1 : INT5 0: PORT 1:SCLK0 0: PORT 1: RXD0 0: PORT 1: TXD0 0 : PORT 1 : TB6IN1 0: PORT 1: TB6IN0 0: PORT 1: TB5IN1 0: PORT 1: TB5IN0 Page 152 TMPM362F10FG PE3F2 PE2F2 PE1F2 Function PE0F2 0 ...
Page 177
... After reset bit symbol - - After reset bit symbol PE7OD PE6OD After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PE7OD to R CMOS PE0OD 1 : Open-drain Function PE5OD PE4OD PE3OD Function Page 153 TMPM362F10FG PE2OD PE1OD PE0OD ...
Page 178
... PE7IE After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PE7IE to PE0IE R PE6UP PE5UP PE4UP Read as 0. Pull-up 0: Disable 1: Enable PE6IE PE5IE PE4IE Read as 0. Intput 0: Disable 1: Enable Page 154 TMPM362F10FG PE3UP PE2UP PE1UP Function PE3IE PE2IE PE1IE Function PE0UP ...
Page 179
... Port F output control register Port F function register 1 Port F open drain control register Port F pull-up control register Port F input control register − Base Address = 0x400C_0500 PFDATA PFCR PFFR1 PFOD PFPUP PFIE Page 155 TMPM362F10FG Address (Base+) 0x0000 0x0004 0x0008 0x0028 0x002C 0x0038 ...
Page 180
... After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-5 − R 4-0 PF4C to PF0C R PF4 Read as 0. Port F data register PF4C Read as 0. Output 0: Disable 1: Enable Page 156 TMPM362F10FG PF3 PF2 PF1 Function PF3C PF2C PF1C Function PF0 ...
Page 181
... After reset 0 0 Bit Bit Symbol Type 31-5 − R Read PF4F1 R/W 0: PORT 1: TRACEDATA3 3 PF3F1 R/W 0: PORT 1: TRACEDATA2 2 PF2F1 R/W 0: PORT 1: TRACEDATA1 1 PF1F1 R/W 0: PORT 1: TRACEDATA0 / SWV 0 PF0F1 R/W 0: PORT 1: TRACECLK PF4F1 PF3F1 PF2F1 Function Page 157 TMPM362F10FG PF1F1 PF0F1 ...
Page 182
... After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-5 − R 4-0 PF4UP to R/W PF0UP PF4OD PF3OD Read CMOS 1 : Open-drain PF4UP PF3UP Read as 0. Pull-up 0: Disable 1: Enable Page 158 TMPM362F10FG PF2OD PF1OD PF0OD Function PF2UP PF1UP PF0UP Function ...
Page 183
... After reset bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-5 − R Read as 0. 4-0 PF4IE to PF0IE R/W Input 0: Disable 1: Enable PF4IE PF3IE PF2IE Function Page 159 TMPM362F10FG PF1IE PF0IE ...
Page 184
... Port G open drain control register Port G pull-up control register Port G input control register Register name PGDATA PGCR PGFR1 PGFR2 PGFR3 PGOD PGPUP PGIE Page 160 TMPM362F10FG T10 T9 T8 Base Address = 0x400C_0600 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0010 0x0028 0x002C 0x0038 0 T8 ...
Page 185
... After reset bit symbol PG7C PG6C After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PG7C to PG0C R/W Output 0: Disable 1: Enable PG5 PG4 PG3 Function PG5C PG4C PG3C Function Page 161 TMPM362F10FG PG2 PG1 PG0 PG2C PG1C PG0C ...
Page 186
... PG4F1 R/W 3 PG3F1 R/W 2 PG2F1 R/W 1 PG1F1 R/W 0 PG0F1 R PG6F1 PG5F1 PG4F1 Read PORT 1:INT7 0: PORT 1: SCK2 0: PORT 1: SCL2 / SI2 0: PORT 1: SDA2 / SO2 0: PORT 1: INT6 0: PORT 1: SCK1 0: PORT 1: SCL1 / SI1 0: PORT 1: SDA1 / SO1 Page 162 TMPM362F10FG PG3F1 PG2F1 PG1F1 Function PG0F1 0 ...
Page 187
... After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-6 − R/W Write PG5F2 R/W 0: PORT 1: TB9IN1 4 PG4F2 R/W 0: PORT 1: TB9IN0 3-2 − R Read PG1F2 R/W 0: PORT 1: TB7IN1 0 PG0F2 R/W 0: PORT 1: TB7IN0 PG5F2 PG4F2 - Function Page 163 TMPM362F10FG PG1F2 PG0F2 ...
Page 188
... PG7F3 After reset 0 Bit Bit Symbol Type 31-8 − PG7F3 R/W 6 PG6F3 R/W 5-4 − PG3F3 R/W 2 PG2F3 R − PG6F3 - - Read PORT 1 : WDTOUT 0 : PORT 1 : CS3 Read PORT 1 : CS1 0 : PORT 1 : CS0 Read as 0. Page 164 TMPM362F10FG PG3F3 PG2F3 - Function ...
Page 189
... After reset bit symbol PG7UP PG6UP After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PG7UP to R/W Pull-up PG0UP 0: Disable 1: Enable PG5OD PG4OD PG3OD Function PG5UP PG4UP PG3UP Function Page 165 TMPM362F10FG PG2OD PG1OD PG0OD PG2UP PG1UP PG0UP ...
Page 190
... After reset 0 15 bit symbol - After reset 0 7 bit symbol PG7IE After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PG7IE to R/W PG0IE PG6IE PG5IE PG4IE Read as 0. Input 0: Disable 1: Enable Page 166 TMPM362F10FG PG3IE PG2IE PG1IE Function PG0IE 0 ...
Page 191
... Port H function register 2 Port H open drain control register Port H pull-upcontrol register Port H input control register T12 T12 T13 T12 Base Address = 0x400C_0700 PHDATA PHCR PHFR1 PHFR2 PHOD PHPUP PHIE Page 167 TMPM362F10FG T12 T12 Address (Base+) 0x0000 0x0004 0x0008 0x000C 0x0028 0x002C 0x0038 ...
Page 192
... PH7C After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PH7C to PH0C R PH6 PH5 PH4 Read as 0. Port H data register PH6C PH5C PH4C Read as 0. Output 0: Disable 1: Enable Page 168 TMPM362F10FG PH3 PH2 PH1 Function PH3C PH2C PH1C Function PH0 ...
Page 193
... R/W 0: PORT 1: SCK4 5 PH5F1 R/W 0: PORT 1: SCL4 / SI4 4 PH4F1 R/W 0: PORT 1: SDA4 / SO4 3 PH3F1 R/W 0: PORT 1: INTC 2 PH2F1 R/W 0: PORT 1: SCK3 1 PH1F1 R/W 0: PORT 1: SCL3 / SI3 0 PH0F1 R/W 0: PORT 1: SDA3 / SO3 PH5F1 PH4F1 PH3F1 Function Page 169 TMPM362F10FG PH2F1 PH1F1 PH0F1 ...
Page 194
... PH6F2 R/W 5 PH5F2 R/W 4 PH4F2 R/W 3 PH3F2 R/W 2 PH2F2 R/W 1 PH1F2 R/W 0 PH0F2 R PH6F2 PH5F2 PH4F2 Read PORT 1: TBEIN1 0: PORT 1: TBEIN0 0: PORT 1: TBDIN1 0: PORT 1: TBDIN0 0: PORT 1: TBBIN1 0: PORT 1: TBBIN0 0: PORT 1: TBAIN1 0: PORT 1: TBAIN0 Page 170 TMPM362F10FG PH3F2 PH2F2 PH1F2 Function PH0F2 0 ...
Page 195
... After reset bit symbol PH7UP PH6UP After reset 0 0 Bit Bit Symbol Type 31-8 − R Read as 0. 7-0 PH7UP to R/W Pull-up PH0UP 0: Disable 1: Enable PH5OD PH4OD PH3OD Function PH5UP PH4UP PH3UP Function Page 171 TMPM362F10FG PH2OD PH1OD PH0OD PH2UP PH1UP PH0UP ...
Page 196
... After reset 0 15 bit symbol - After reset 0 7 bit symbol PH7IE After reset 0 Bit Bit Symbol Type 31-8 − R 7-0 PH7IE to R/W PH0IE PH6IE PH5IE PH4IE Read as 0. Input 0: Disable 1: Enable Page 172 TMPM362F10FG PH3IE PH2IE PH1IE Function PH0IE 0 ...
Page 197
... Port I function register 1 Port I open drain control register Port I pull-up control register Port I input control register − − T16 T16 Base Address = 0x400C_0800 PIDATA PICR PIFR1 PIOD PIPUP PIIE Page 173 TMPM362F10FG 1 0 T15 T14 Address (Base+) 0x0000 0x0004 0x0008 0x0028 0x002C 0x0038 ...
Page 198
... After reset 0 23 bit symbol - After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-4 − R 3-0 PI3 to PI0 R Read as 0. Port I data register Page 174 TMPM362F10FG PI3 PI2 PI1 Function PI0 0 ...
Page 199
... PICR (Port I output control register bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset bit symbol - - After reset 0 0 Bit Bit Symbol Type 31-4 − R Read as 0. 3-0 PI3C-PI0C R/W Output 0: Disable 1: Enable PI3C PI2C Function Page 175 TMPM362F10FG PI1C PI0C ...
Page 200
... After reset 0 15 bit symbol - After reset 0 7 bit symbol - After reset 0 Bit Bit Symbol Type 31-4 − PI3F1 R/W 2 PI2F1 R/W 1 PI1F1 R/W 0 − R Read PORT 1: INTF 0: PORT 1: INTE 0: PORT 1: CEC Write as 0. Page 176 TMPM362F10FG PI3F1 PI2F1 PI1F1 Function ...