TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 485

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

14.5.9
14.5.10
is generated after the SCL line is released.
on the bus (the bus is busy), and cleared to "0" when the stop condition is detected (the bus is free).
clock cycles set by <BC> and <ACK> is completed.
matches the values specified at SBIxI2CAR or when a general-call (eight bits data following the start condi-
tion is all "0") is received.
cleared to "0", the SBI pulls the SCL line to the "Low" level.
line to be released after <PIN> is set to "1". When the program writes "1" to <PIN>, it is set to "1". Howev-
er, writing "0" does not clear this bit to "0".
arbitration procedure to ensure correct data transfer.
start condition occurring on the SDA and SCL lines.The I2C-bus arbitration takes place on the SDA line.
If SCL bus line is pulled "Low" by other devices when the stop condition is generated, the stop condition
SBIxSR<BB> can be read to check the bus state. <BB> is set to "1" when the start condition is detected
In master mode, a serial bus interface request (INTSBIx) is generated when the transfer of the number of
In slave mode, INTSBIx is generated under the following conditions.
In the address recognition mode (<ALS> = "0"), INTSBIx is generated when the received slave address
When an interrupt request (INTSBIx) is generated, SBIxCR2<PIN> is cleared to "0". While <PIN> is
<PIN> is set to "1" when data is written to or read from SBIxDBR. It takes a period of t
The I2C bus has the multi-master capability (there are two or more masters on a bus), and requires the bus
A master that attempts to generate the start condition while the bus is busy loses bus arbitration, with no
The arbitration procedure for two masters on a bus is shown below.
Interrupt Service Request and Release
Note:When arbitration is lost in master mode, <PIN> is not cleared to "0" if the slave address does not
Arbitration Lost Detection Monitor
・ After output of the acknowledge signal which is generated when the received slave address match-
・ After the acknowledge signal is generated when a general-call address is received.
・ When the slave address matches or a data transfer is completed after receiving a general-call address.
es the slave address set to SBIxI2CAR<SA[6:0]>.
match (INTSBIx is generated).
Figure 14-6 Generating the Stop Condition
SCL line
SDA line
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Stop condition
TMPM362F10FG
LOW
for the SCL