TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 90

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

7.1
Overview
7.1.2.3
user.
cur again upon return to normal program execution.
the currently executing ISR and services the newly detected exception.
An ISR performs necessary processing for the corresponding exception. ISRs must be prepared by the
An ISR may need to include code for clearing the interrupt request so that the same interrupt will not oc-
For details about interrupt handling, see "7.5 Interrupts".
If a higher priority exception occurs during ISR execution for the current exception, the CPU abandons
Executing an ISR
and Hard Fault ISR address). Set ISR addresses for other exceptions if necessary.
0x00
0x04
0x08
0x0C
0x10
0x14
0x18
0x1C to 0x28
0x2C
0x30
0x34
0x38
0x3C
0x40
You must always set the first four words (stack top address, reset ISR address, NMI ISR address,
Offset
Reset
Reset
Non-Maskable Interrupt
Hard Fault
Memory Management
Bus Fault
Usage Fault
Reserved
SVCall
Debug Monitor
Reserved
PendSV
SysTick
External Interrupt
Exception
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Initial value of the main stack
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
ISR address
Contents
Required
Required
Required
Required
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Optional
Setting
TMPM362F10FG