TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 511

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

15. Consumer Electronics Control (CEC)
15.1
15.1.1
15.1.2
15.1.3
red to as CEC) protocol.
The CEC function transmits and receives data that conforms to Consumer Electronics Control (hereafter refer-
It can operate conformably to HDMI 1.3a specifications.
Outline
tor sends a new message beginning with the start bit without having sent the last block with EOM="1", a max-
imum cycle error is determined for the ACK bit and an interrupt is generated. Then, the receive operation is per-
formed in the usual way.
When data reception at logical address discrepancy is enabled(CECRCR1<CECOTH> = "1"), if the initia-
Reception
Transmission
Precautions
・ Clock sampling at fs clock or TBxOUT which is output of 16bit Timer/Event counters
・ Data reception per 1byte
・ Error detection
・ Data transmission per 1byte
・ Flexible waveform
・ Error detection
-Adjustable noise canceling time
-Flexible data sampling point
-Data reception is available even when an address discrepancy is detected.
-Cycle error (min./max.)
-ACK collision
-Waveform error
-Triggered by auto-detection of bus free state
-Adjustable rising edge and cycle
-Arbitration lost
-ACK response error
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TMPM362F10FG