TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 21

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

19. Backup module
20. Analog / Digital Converter (ADC)
18.3 Register in detail..................................................................................................................556
18.4 Key-on Wakeup Operation..................................................................................................564
18.5 Pull-up Function..................................................................................................................565
18.6 KWUP input Detection Timing..........................................................................................567
19.1 Features................................................................................................................................569
19.2 Block Diagram.....................................................................................................................569
19.3 BACKUP Mode Operation.................................................................................................570
20.1 Outline.................................................................................................................................575
20.2 Configuration.......................................................................................................................576
20.3 Registers..............................................................................................................................577
20.4 Description of Operations...................................................................................................598
18.3.1
18.3.2
18.3.3
18.3.4
18.3.5
18.3.6
18.3.7
18.3.8
18.3.9
18.5.1
18.5.2
19.3.1
20.3.1
20.3.2
20.3.3
20.3.4
20.3.5
20.3.6
20.3.7
20.3.8
20.3.9
20.3.10
20.3.11
20.3.12
20.3.13
20.3.14
20.3.15
20.3.16
20.3.17
20.3.18
20.3.19
20.3.20
20.4.1
20.4.2
20.4.3
20.4.4
20.4.5
19.3.1.1
19.3.1.2
19.3.1.3
19.3.1.4
20.4.2.1
20.4.2.2
Register list....................................................................................................................................................................556
KWUPCR0 (Control register 0)....................................................................................................................................556
KWUPCR1 (Control register 1)....................................................................................................................................557
KWUPCR2 (Control register 2)....................................................................................................................................558
KWUPCR3 (Control register 3)....................................................................................................................................559
KWUPPKEY (Port monitor register)...........................................................................................................................560
KWUPCNT (Pull-up cycle register).............................................................................................................................561
KWUPCLR (All interrupt request clear register).........................................................................................................562
KWUPINT (Interrupt monitor register)........................................................................................................................563
In case of using KWUP inputs with pull-up enabled...................................................................................................565
In case of using KWUP inputs with pull-up disabled..................................................................................................566
Operable peripherals in the BACKUP mode................................................................................................................570
Register list....................................................................................................................................................................577
ADCBAS (Conversion Accuracy Setting Register).....................................................................................................578
ADCLK (Conversion Clock Setting Register).............................................................................................................579
ADMOD0 (Mode Control Register 0)..........................................................................................................................581
ADMOD1 (Mode Control Register 1)..........................................................................................................................582
ADMOD2 (Mode Control Register 2) .........................................................................................................................583
ADMOD3 (Mode Control Register 3)..........................................................................................................................585
ADMOD4 (Mode Control Register 4) .........................................................................................................................586
ADMOD5 (Mode Control Register 5)..........................................................................................................................587
Analog Reference Voltage............................................................................................................................................598
AD Conversion Mode...................................................................................................................................................598
AD Monitor Function....................................................................................................................................................599
Selecting the Input Channel..........................................................................................................................................600
AD Conversion Details.................................................................................................................................................600
ADREG08 (Conversion Result Register 08)..............................................................................................................588
ADREG19 (AD Conversion Result Register 19).......................................................................................................589
ADREG2A (AD Conversion Result Register 2A).....................................................................................................590
ADREG3B (AD Conversion Result Register 3B)......................................................................................................591
ADREG4C (AD Conversion Result Register 4C)......................................................................................................592
ADREG5D (AD Conversion Result Register 5D).....................................................................................................593
ADREG6E (AD Conversion Result Register 6E)......................................................................................................594
ADREG7F (AD Conversion Result Register 7F).......................................................................................................595
ADREGSP (AD Conversion Result Register SP)......................................................................................................596
ADCMP0 (AD Conversion Result Comparison Register 0)......................................................................................597
ADCMP1 (AD Conversion Result Comparison Register 1)......................................................................................597
Transition to the BACKUP mode
Backup Transition Flow
Transition Flowchart
BACKUP Mode Timing Chart
Normal AD conversion
Top-priority AD conversion
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