TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 132

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

7.6
Exception / Interrupt-Related Registers
14-12
11-10
9
8
7
6-4
3-2
1
0
Bit
Note 1: <EMSTx> is effective only when <EMCGx[2:0]> is set to "100" for both rising and falling edge. The active level used
Note 2: Please specify the bit for the edge first and then specify the bit for the <INTxEN>. Setting them simultaneously is pro-
EMCG1[2:0]
EMST1[1:0]
−
INT1EN
−
EMCG0[2:0]
EMST0[1:0]
−
INT0EN
Bit Symbol
for the reset of standby can be checked by referring <EMSTx>. If interrupts are cleared with the CGICRCG register,
<EMSTx> is also cleared.
hibited.
R/W
R
R
R/W
R
R/W
R
R
R/W
Type
active level setting of INT1 standby clear request. (101 to 111: setting prohibited)
000: "Low" level
001: "High" level
010: Falling edge
011: Rising edge
100: Both edge
active level of INT1 standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edge
Reads as undefined.
INT1 clear input
0: Disable
1: Enable
Read as 0,
active level setting of INT0 standby clear request. (101 to 111: setting prohibited)
000: "Low" level
001: "High" level
010: Falling edge
011: Rising edge
100: Both edge
active level of INT0 standby clear request
00: −
01: Rising edge
10: Falling edge
11: Both edge
Reads as undefined.
INT0 clear input
0: Disable
1: Enable
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Function
TMPM362F10FG