TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 423

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

12.11.3.3
12.11.3.4
12.11.3.5
ed in the receive buffer and FIFO. Thus, in this mode, the overrun error flag has no meaning.
ing. In the case of the next data can be received in the receive shift register before reading a data from
the receive buffer. The parity bit to be added in the 8-bit UART mode as well as the most significant bit
in the 9-bit UART mode will be stored in SCxCR<RB8>.
be stored in FIFO. In the 8-bit UART mode, the parity bit is lost but parity error is determined and the re-
sult is stored in SCxCR<PERR>.
up function SCxMOD0 <WU> to "1". In this case, the interrupt INTRXx will be generated only when
SCxCR<RB8> is set to "1".
(1)
(2)
(3)
In the I/O interface mode and SCLK output setting, SCLK output stops when all received data is stor-
The timing of SCLK output stop and re-output depends on receive buffer and FIFO.
In spite of enabling or disabling FIFO, read the received data from the receive buffer (SCxBUF).
When receive FIFO is disabled, the buffer full flag SCxMOD2<RBFLL> is cleared to "0" by this read-
When the receive FIFO is available, the 9-bit UART mode is prohibited because up to 8-bit data can
In the 9-bit UART mode, the slave controller can be operated in the wake-up mode by setting the wake-
I/O interface mode with SCLK output
Read Received Data
Wake-up Function
the transfer device by hand-shake.
in the receive shift register is transferred into the received buffer and SCLK output restarts.
ing SCxMOD0<RXE> bit, too.
Stop SCLK output after receiving a data. In this mode, I/O interface can transfer each data with
When the data in a buffer is read, SCLK output restarts.
Stop SCLK output after receiving the data into a receive shift register and a receive buffer.
When the data is read, SCLK output restarts.
Stop SCLK output after receiving the data into a shift register, received buffer and FIFO.
When one byte data is read, the data in the received buffer is transferred into FIFO and the data
And if SCxFCNF<RXTXCNT>is set to "1", SCLK stops and receive operation stops with clear-
Case of single buffer
Case of double buffer
Case of FIFO
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TMPM362F10FG