TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 305

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

9.4.4
31-2
1
0
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
bit symbol
After reset
Bit
-
IntTCClear1
IntTCClear0
DMACIntTCClear (DMAC Interrupt Terminal Count Clear Register)
Bit Symbol
Undefined
Undefined
Undefined
Undefined
31
23
15
7
-
-
-
-
W
W
W
Type
Undefined
Undefined
Undefined
Undefined
30
22
14
6
Write as zero.
Clear DMAC channel 1 transfer end interrupt.
0 : Invalid
1 : Clear
The DMACIntTCStatus<IntTCStatus1> will be cleared when "1" is written.
Clear DMAC channel 0 transfer end interrupt.
0 : Invalid
1 : Clear
The DMACIntTCStatus<IntTCStatus0> will be cleared when "1" is written.
-
-
-
-
Undefined
Undefined
Undefined
Undefined
29
21
13
5
-
-
-
-
Page 281
Undefined
Undefined
Undefined
Undefined
28
20
12
4
-
-
-
-
Undefined
Undefined
Undefined
Undefined
Description
27
19
11
3
-
-
-
-
Undefined
Undefined
Undefined
Undefined
26
18
10
2
-
-
-
-
IntTCClear1
Undefined
Undefined
Undefined
25
17
9
1
0
-
-
-
TMPM362F10FG
IntTCClear0
Undefined
Undefined
Undefined
24
16
8
0
0
-
-
-