TMPM362F10FG Toshiba, TMPM362F10FG Datasheet - Page 460

• Manufacturer Part Number: TMPM362F10FG
• Description: 32BIT MICROCONTROLLER
• Manufacturer: Toshiba
• Series: TX03r

Specifications of TMPM362F10FG

• Core Processor: ARM® Cortex-M3™
• Core Size: 32-Bit
• Speed: 64MHz
• Connectivity: I²C, Microwire, SIO, SPI, SSP, UART/USART
• Peripherals: DMA, WDT
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Package / Case: 144-LQFP
• Processor Series: TX03
• Core: ARM Cortex M3
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Product Summaries: Summary
• Lead Free: Yes
• Rohs Compatible Product(s): Available
• Rom (kbytes): 1024K
• Rom Type: Flash
• Ram (kbytes): 64K
• Number Of Pins: 144
• Package: LQFP(20x20)
• Vcc: 3V
• Cpu Mhz: 64
• Ssp (ch) Spi: 1
• I2c/sio (ch): 5
• Uart/sio (ch): 12
• Usb: -
• Can: -
• Ethernet: -
• External Bus Interface: Y
• Cs/wait Controller (ch): 4
• Dma Controller: 2
• 10-bit Da Converter: -
• 10-bit Ad Converter: 16
• 12-bit Ad Converter: -
• 16-bit Timer / Counter: 16
• Motor / Igbt Control: -
• Real Time Clock: 1
• Watchdog Timer: Y
• Osc Freq Detect: -
• Clock Gear: Y
• Low-power Hold Function: Y
• Remote Control Interface: Y
• Hardware Cec Controller: Y
• Comparators: -
• Low-voltage Detector: -
• Etm Hardware Trace: 4-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Number Of I /o: -
• Eeprom Size: -
• Oscillator Type: -
• Lead Free Status / Rohs Status: Details
• Other names: Q5704184A

13.4
Overview of SSP
13.4.4
rupts is asserted, the combined interrupt INTSSP is asserted.
Pre-enable receive overrun interrupt
The High active interrupts, each of which can be masked separately, are generated.
Also, The individual masked sources are combined into a single interrupt. When any of the above inter-
Interrupt generation logic
Transmit interrupt
Time-out interrupt
a. Transmit interrupt
b. Receive interrupt
c. Time-out interrupt
Receive interrupt
Overrun interrupt
Pre-enable transmit interrupt
Pre-enable timeout interrupt
Pre-enable receive interrupt
The transmit interrupt is also generated when the SSP operation is disabled (SSPCR1 <SSE> = "0").
idle for a fixed 32-bit period (bit rate). This mechanism ensures that the user is aware that data is
still present in the receive FIFO and requires servicing. This operation occurs in both master and
slave modes. When the time-out interrupt is generated, read all data from the receive FIFO. Even if
all the data is not read, data can be transmitted / received if the receive FIFO has a free space and
the number of data to be transmitted does not exceed the free space of the receive FIFO. When trans-
fer starts, the timeout interrupt will be cleared. If data is transmitted / received when the receive
FIFO has no free space, the time-out interrupt will not be cleared and an overrun interrupt will be gen-
erated.
The transmit interrupt is asserted when there are four or fewer valid entries in the transmit FIFO.
The first transmitted data can be written in the FIFO by using this interrupt.
The receive interrupt is asserted when there are four or more valid entries in the receive FIFO.
The time-out interrupt is asserted when the receive FIFO is not empty and the SSP has remained
RORIM(mask
TXIM mask
RXIM(mask
RTM(mask
A conditional interrupt to occur when the transmit FIFO has free space more than (includ-
ing half) of the entire capacity.
(Number of valid data items in the transmit FIFO ≤ 4)
A conditional interrupt to occur when the receive FIFO has valid data more than half (includ-
ing half) the entire capacity.
(Number of valid data items in the receive FIFO ≥ 4)
A conditional interrupt to indicate that the data exists in the receive FIFO to the time-out pe-
riod.
Conditional interrupts indicating that data is written to receive FIFO when it is full.
Post-enable transmit interrupt
Post-enable receive interrupt
Post-enable
receive timeout interrupt
Post-enable
receive overrun interrupt
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TMPM362F10FG
INTSSP