ATA5773-PXQW Atmel, ATA5773-PXQW Datasheet - Page 114
ATA5773-PXQW
Manufacturer Part Number
ATA5773-PXQW
Description
XMITTR UHF ASK/FSK 310MHZ 24VQFN
Manufacturer
Atmel
Datasheet
1.ATA5773-DK1.pdf
(219 pages)
Specifications of ATA5773-PXQW
Frequency
310MHz ~ 350MHz
Modulation Or Protocol
UHF
Power - Output
8dBm
Voltage - Supply
2 V ~ 4 V
Current - Transmitting
9.8mA
Data Interface
PCB, Surface Mount
Memory Size
4kB Flash, 256B EEPROM, 256B SRAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
Processor Series
ATA5x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
4 KB
Data Ram Size
256 B
Interface Type
SPI, USI
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Receiving
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA5773-PXQW
Manufacturer:
ATMEL
Quantity:
3 500
Part Number:
ATA5773-PXQW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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4.16.10
114
Atmel ATA5771/73/74
Timer/Counter Timing Diagrams
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOT-
TOM the output will be continuously low and if set equal to TOP the output will be set to high
for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when interrupt
flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for
modes utilizing double buffering).
OCF1x.
Figure 4-46. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
Figure 4-47
Figure 4-47. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f
TCNTn
OCRnx
OCFnx
OCRnx
(clk
TCNTn
OCFnx
(clk
clk
clk
clk
clk
I/O
I/O
I/O
Tn
I/O
Tn
/1)
/8)
shows the same timing data, but with the prescaler enabled.
OCRnx - 1
OCRnx - 1
Figure 4-46
OCRnx
OCRnx
OCRnx Value
OCRnx Value
shows a timing diagram for the setting of
OCRnx + 1
OCRnx + 1
T1
) is therefore shown as a
OCRnx + 2
OCRnx + 2
9137E–RKE–12/10
clk_I/O
/8)
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