ATA5773-PXQW Atmel, ATA5773-PXQW Datasheet - Page 124
ATA5773-PXQW
Manufacturer Part Number
ATA5773-PXQW
Description
XMITTR UHF ASK/FSK 310MHZ 24VQFN
Manufacturer
Atmel
Datasheet
1.ATA5773-DK1.pdf
(219 pages)
Specifications of ATA5773-PXQW
Frequency
310MHz ~ 350MHz
Modulation Or Protocol
UHF
Power - Output
8dBm
Voltage - Supply
2 V ~ 4 V
Current - Transmitting
9.8mA
Data Interface
PCB, Surface Mount
Memory Size
4kB Flash, 256B EEPROM, 256B SRAM
Antenna Connector
PCB, Surface Mount
Operating Temperature
-40°C ~ 85°C
Package / Case
24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
Processor Series
ATA5x
Core
AVR8
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
4 KB
Data Ram Size
256 B
Interface Type
SPI, USI
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
12
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Applications
-
Sensitivity
-
Data Rate - Maximum
-
Current - Receiving
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATA5773-PXQW
Manufacturer:
ATMEL
Quantity:
3 500
Part Number:
ATA5773-PXQW
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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4.17.2
4.17.2.1
124
Atmel ATA5771/73/74
Register Description
GTCCR – General Timer/Counter Control Register
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the
system clock frequency (f
uses sampling, the maximum frequency of an external clock it can detect is half the sampling
frequency (Nyquist sampling theorem). However, due to variation of the system clock fre-
quency and duty cycle caused by Oscillator source (crystal, resonator, and capacitors)
tolerances, it is recommended that maximum frequency of an external clock source is less
than f
An external clock source can not be prescaled.
Figure 4-51. Prescaler for Timer/Counter0
Note:
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode,
the value that is written to the PSR10 bit is kept, hence keeping the Prescaler Reset signal
asserted. This ensures that the Timer/Counter is halted and can be configured without the risk
of advancing during configuration. When the TSM bit is written to zero, the PSR10 bit is
cleared by hardware, and the Timer/Counter start counting.
• Bit 0 – PSR10: Prescaler 0 Reset Timer/Counter n
When this bit is one, the Timer/Countern prescaler will be Reset. This bit is normally cleared
immediately by hardware, except if the TSM bit is set.
Bit
0x23 (0x43)
Read/Write
Initial Value
clk_I/O
1. The synchronization logic on the input pins (
/2.5.
PSR10
clk
T0
I/O
TSM
R/W
7
0
Synchronization
R
6
–
0
ExtClk
< f
Clear
clk_I/O
R
5
–
0
/2) given a 50/50% duty cycle. Since the edge detector
R
4
–
0
T0)
R
3
–
0
is shown in
R
2
–
0
clk
Figure 4-50 on page 123
T0
R
1
–
0
PSR10
R/W
0
0
9137E–RKE–12/10
GTCCR
.
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