A3P125-FGG144 Actel, A3P125-FGG144 Datasheet - Page 13

• Manufacturer Part Number: A3P125-FGG144
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of A3P125-FGG144

• Processor Series: A3P125
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 125 K
• Package / Case: FPBGA-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I/Os with Advanced I/O Standards
The ProASIC3 family of FPGAs features a flexible I/O structure, supporting a range of voltages (1.5 V,
1.8 V, 2.5 V, and 3.3 V). ProASIC3 FPGAs support many different I/O standards—single-ended and
differential.
The I/Os are organized into banks, with two or four banks per device. The configuration of these banks
determines the I/O standards supported
Table 1-1 • I/O Standards Supported
Each I/O module contains several input, output, and enable registers. These registers allow the
implementation of the following:
ProASIC3 banks for the A3P250 device and above support LVPECL, LVDS, B-LVDS and M-LVDS.
B-LVDS and M-LVDS can support up to 20 loads.
Hot-swap (also called hot-plug, or hot-insertion) is the operation of hot-insertion or hot-removal of a card
in a powered-up system.
Cold-sparing (also called cold-swap) refers to the ability of a device to leave system data undisturbed
when the system is powered up, while the component itself is powered down, or when power supplies
are floating.
Wide Range I/O Support
Actel ProASIC3 devices support JEDEC-defined wide range I/O operation. ProASIC3 supports the
JESD8-B specification, covering both 3 V and 3.3 V supplies, for an effective operating range of 2.7 V to
3.6 V.
Wider I/O range means designers can eliminate power supplies or power conditioning components from
the board or move to less costly components with greater tolerances. Wide range eases I/O bank
management and provides enhanced protection from system voltage spikes, while providing the
flexibility to easily run custom voltage applications.
I/O Bank Type
Advanced
Standard Plus
Standard
•
•
Single-Data-Rate applications
Double-Data-Rate applications—DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point
communications
East and west Banks of A3P250 and
larger devices
North and south banks of A3P250 and
larger devices
All banks of A3P060 and A3P125
All banks of A3P015 and A3P030
Device and Bank Location
(Table
R e v i s i o n 9
1-1).
LVCMOS PCI/PCI-X
LVTTL/
✓
✓
✓
I/O Standards Supported
supported
ProASIC3 Flash Family FPGAs
Not
✓
✓
B-LVDS, M-LVDS
LVPECL, LVDS,
Not supported
Not supported
✓
1 -7