A3P125-FGG144 Actel, A3P125-FGG144 Datasheet - Page 51

• Manufacturer Part Number: A3P125-FGG144
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of A3P125-FGG144

• Processor Series: A3P125
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 125 K
• Package / Case: FPBGA-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-44 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew
Table 2-45 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Drive
Strength
4 mA
6 mA
8 mA
12 mA
16 mA
Note:
Drive
Strength
2 mA
4 mA
6 mA
8 mA
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Applicable to Standard Plus I/O Banks
Commercial-Case Conditions: T
Applicable to Standard I/O Banks
Speed
Grade
Std.
Std.
Std.
Std.
Std.
–1
–2
–1
–2
–1
–2
–1
–2
–1
–2
Speed
Grade
Std.
Std.
Std.
Std.
–1
–2
–1
–2
–1
–2
–1
–2
t
DOUT
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
t
DOUT
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
0.66
0.56
0.49
9.68
8.23
7.23
6.70
5.70
5.00
6.70
5.70
5.00
5.05
4.29
3.77
5.05
4.29
3.77
t
DP
7.07
6.01
5.28
7.07
6.01
5.28
4.41
3.75
3.29
4.41
3.75
3.29
t
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
t
DP
DIN
J
J
1.00
0.85
0.75
1.00
0.85
0.75
1.00
0.85
0.75
1.00
0.85
0.75
1.00
0.85
0.75
t
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
0.04
0.04
0.03
t
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
PY
DIN
t
EOUT
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
1.00
0.85
0.75
1.00
0.85
0.75
1.00
0.85
0.75
1.00
0.85
0.75
t
PY
R e v i s i o n 9
9.86
8.39
7.36
6.82
5.80
5.10
6.82
5.80
5.10
5.14
4.37
3.84
5.14
4.37
3.84
t
ZL
t
EOUT
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
0.43
0.36
0.32
Table 2-6 on page 2-6
8.42
7.17
6.29
5.89
5.01
4.40
5.89
5.01
4.40
4.51
3.84
3.37
4.51
3.84
3.37
t
ZH
Table 2-6 on page 2-6
7.20
6.12
5.37
7.20
6.12
5.37
4.49
3.82
3.36
4.49
3.82
3.36
t
ZL
2.28
1.94
1.70
2.58
2.20
1.93
2.58
2.20
1.93
2.79
2.38
2.09
2.79
2.38
2.09
t
LZ
6.23
5.30
4.65
6.23
5.30
4.65
3.75
3.19
2.80
3.75
3.19
2.80
t
ZH
2.21
1.88
1.65
2.74
2.33
2.05
2.74
2.33
2.05
3.08
2.62
2.30
3.08
2.62
2.30
t
HZ
for derating values.
ProASIC3 Flash Family FPGAs
2.07
1.76
1.55
2.07
1.76
1.55
2.39
2.04
1.79
2.39
2.04
1.79
t
12.09
10.29
LZ
9.03
9.06
7.71
6.76
9.06
7.71
6.76
7.38
6.28
5.51
7.38
6.28
5.51
t
ZLS
for derating values.
2.15
1.83
1.60
2.15
1.83
1.60
2.69
2.29
2.01
2.69
2.29
2.01
t
10.66
HZ
t
9.07
7.96
8.12
6.91
6.06
8.12
6.91
6.06
6.75
5.74
5.04
6.75
5.74
5.04
ZHS
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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