A3P125-FGG144 Actel, A3P125-FGG144 Datasheet - Page 89

• Manufacturer Part Number: A3P125-FGG144
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of A3P125-FGG144

• Processor Series: A3P125
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 125 K
• Package / Case: FPBGA-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-16 • Input Register Timing Diagram
Table 2-98 • Input Data Register Propagation Delays
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
Enable
Data
Clear
CLK
Preset
Out_1
ICLKQ
ISUD
IHD
ISUE
IHE
ICLR2Q
IPRE2Q
IREMCLR
IRECCLR
IREMPRE
IRECPRE
IWCLR
IWPRE
ICKMPWH
ICKMPWL
For specific junction temperature and voltage supply levels, refer to
Commercial-Case Conditions: T
Clock-to-Q of the Input Data Register
Data Setup Time for the Input Data Register
Data Hold Time for the Input Data Register
Enable Setup Time for the Input Data Register
Enable Hold Time for the Input Data Register
Asynchronous Clear-to-Q of the Input Data Register
Asynchronous Preset-to-Q of the Input Data Register
Asynchronous Clear Removal Time for the Input Data Register
Asynchronous Clear Recovery Time for the Input Data Register
Asynchronous Preset Removal Time for the Input Data Register
Asynchronous Preset Recovery Time for the Input Data Register
Asynchronous Clear Minimum Pulse Width for the Input Data Register
Asynchronous Preset Minimum Pulse Width for the Input Data Register
Clock Minimum Pulse Width High for the Input Data Register
Clock Minimum Pulse Width Low for the Input Data Register
Input Register
Timing Characteristics
50%
50%
t
1
ISUE
t
IHE
50%
50%
t
ISUD
0
t
ICLKQ
t
IHD
50%
50%
J
Description
50%
= 70°C, Worst-Case VCC = 1.425 V
t
IWPRE
t
IPRE2Q
50%
50%
t
R e v i s i o n 9
IRECPRE
50%
t
ICLR2Q
50%
t
IWCLR
50%
50%
50%
Table 2-6 on page 2-6
t
IRECCLR
50%
t
ICKMPWH
ProASIC3 Flash Family FPGAs
t
IREMPRE
50%
0.00 0.00 0.00
0.45 0.52 0.61
0.36 0.41 0.48
0.24 0.27 0.32
0.26 0.30 0.35
0.00 0.00 0.00
0.37 0.42 0.50
0.45 0.52 0.61
0.00 0.00 0.00
0.22 0.25 0.30
0.00 0.00 0.00
0.22 0.25 0.30
0.22 0.25 0.30
0.22 0.25 0.30
0.32 0.37 0.43
–2
for derating values.
50%
t
ICKMPWL
–1 Std. Units
50%
t
50%
IREMCLR
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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