A3P125-FGG144 Actel, A3P125-FGG144 Datasheet - Page 93

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A3P125-FGG144

Manufacturer Part Number
A3P125-FGG144
Description
FPGA - Field Programmable Gate Array 125K System Gates
Manufacturer
Actel
Datasheet

Specifications of A3P125-FGG144

Processor Series
A3P125
Core
IP Core
Maximum Operating Frequency
350 MHz
Number Of Programmable I/os
133
Data Ram Size
36864
Delay Time
11.1 ns
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
125 K
Package / Case
FPBGA-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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DDR Module Specifications
Input DDR Module
Figure 2-19 • Input DDR Timing Model
Table 2-101 • Parameter Definitions
Parameter Name
t
t
t
t
t
t
t
t
CLK
Data
DDRICLKQ1
DDRICLKQ2
DDRISUD
DDRIHD
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
CLR
INBUF
CLKBUF
INBUF
Clock-to-Out Out_QR
Clock-to-Out Out_QF
Data Setup Time of DDR input
Data Hold Time of DDR input
Clear-to-Out Out_QR
Clear-to-Out Out_QF
Clear Removal
Clear Recovery
A
B
C
Parameter Definition
R e v i s i o n 9
Input DDR
DDR_IN
FF1
FF2
Measuring Nodes (from, to)
ProASIC3 Flash Family FPGAs
D
E
B, D
C, D
C, E
C, B
C, B
B, E
A, B
A, B
Out_QF
(to core)
Out_QR
(to core)
2- 79

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