A3P125-FGG144 Actel, A3P125-FGG144 Datasheet - Page 208

• Manufacturer Part Number: A3P125-FGG144
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of A3P125-FGG144

• Processor Series: A3P125
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 125 K
• Package / Case: FPBGA-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Datasheet Information
4 - 2
Revision
Revision 7 (cont’d)
Revision 6 (Dec 2008)
Packaging v1.4
Revision 5 (Aug 2008)
DC
Characteristics v1.3
Revision 4 (Jun 2008)
DC
Characteristics v1.2
Revision 3 (Jun 2008)
Packaging v1.3
and
and
Switching
Switching
The QN48 package was added to the following tables:
"ProASIC3 Product Family"
"I/Os Per Package
"ProASIC3 FPGAs Package Sizes Dimensions"
"Temperature Grade Offerings"
The number of singled-ended I/Os for QN68 was added to the
Package
The
The
The
TJ, Maximum Junction Temperature, was changed to 100° from 110º in the
"Thermal Characteristics" section
Power Allowed has thus changed to 1.463 W from 1.951 W.
Values for the A3P015 device were added to
Current
Values for the A3P015 device were added to
Contributing to Dynamic Power Consumption in ProASIC3
removed.
Consumption in ProASIC3 Devices
The
from P
Both fall and rise values were included for t
Input DDR Propagation
Table 2-107 • A3P015 Global Resource
The typical value for Delay Increments in Programmable Delay Blocks was
changed from 160 to 200 in
Table note references were added to
Conditions
The title for
remove "as measured on quiet I/Os." Table note 1 was revised to remove
"estimated SSO density over cycles." Table note 2 was revised to remove "refers
only to overshoot/undershoot limits for simultaneous switching I/Os.
The
pertaining to input buffer power and output buffer power.
Table 2-29 • I/O Output Buffer Maximum Resistances
values for 3.3 V PCI/PCI-X.
Table 2-90 • LVDS Minimum and Maximum DC Input and Output Levels
updated.
Pin numbers were added to the
added below the diagram.
The
addition, note 1 was changed from top view to bottom view, and note 2 is new.
"Wide Range I/O Support" section
"48-Pin QFN"
"68-Pin QFN"
"PLL Contribution—PPLL" section
"Power per I/O Pin" section
"132-Pin QFN"
AC13
Characteristics.
1
"
Table 2-15 • Different Components Contributing to the Static Power
1,2
+ P
table.
Table 2-4 • Overshoot and Undershoot Limits
, and the order of the table notes was changed.
AC14
section is new.
pin table for A3P030 is new.
1
"
* F
package diagram was updated to include D1 to D4. In
CLKOUT
Delays.
Table 2-115 • ProASIC3 CCC/PLL
to P
R e vi s i o n 9
"68-Pin QFN"
and
DC4
Changes
is new.
was updated to include 3 additional tables
+ P
is new.
EQ
was updated to change the P
is new.
Table 2-2 • Recommended Operating
AC13
2. The calculated result of Maximum
DDRISUD
Table 2-14 • Different Components
* F
package diagram. Note 2 was
Table 2-7 • Quiescent Supply
CLKOUT
and t
1
.
DDRIHD
was revised to include
Devices. P
1
Specification.
was modified to
in
"
Table 2-102 •
PLL
"I/Os Per
AC14
formula
was
was
2-10,
Page
2-13
2-80
2-88
2-92
2-27
2-68
N/A
1-7
3-1
3-5
2-5
2-6
2-2
2-3
2-6
3-3
3-6
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