A3P125-FGG144 Actel, A3P125-FGG144 Datasheet - Page 207

• Manufacturer Part Number: A3P125-FGG144
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of A3P125-FGG144

• Processor Series: A3P125
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 125 K
• Package / Case: FPBGA-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4 – Datasheet Information
List of Changes
Revision
July 2010
Revision 9 (Oct 2009)
Product Brief v1.3
Packaging v1.5
Revision 8 (Aug 2009)
Product Brief v1.2
DC
Characteristics v1.4
Revision 7 (Feb 2009)
Product Brief v1.1
and
Switching
The following table lists critical changes that were made in each version of the ProASIC3 datasheet.
The
The versioning system for datasheets has been changed. Datasheets are
assigned a revision number that increments each time the datasheet is revised.
The
device in the device family.
The CS121 package was added to
Per Package
"ProASIC3 Ordering
"ProASIC3 Ordering Information"
compliant packages are halogen-free.
All references to M7 devices (CoreMP7) and speed grade –F were removed from
this document.
Table 1-1 • I/O Standards Supported
The
hot-swap and cold-sparing.
3.3 V LVCMOS and 1.2 V LVCMOS Wide Range support was added to the
datasheet. This affects all tables that contained 3.3 V LVCMOS and 1.2 V
LVCMOS data.
I
Maximum DC Input and Output Levels" tables.
–F was removed from the datasheet. The speed grade is no longer supported.
The notes in
Table 2-4 • Overshoot and Undershoot Limits
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays
updated.
In
t
t
In
t
t
In the title of
changed from 3.0 V to 1.7 V.
The
power supply voltage support.
Table 1 • ProASIC3 Product Family
equivalent macrocells for A3P250.
IL
WRO
CCKH
WRO
CCKH
Table 2-116 •
Table 2-117 •
and I
"121-Pin CSP"
"I/Os with Advanced I/O Standards" section
"ProASIC3 Device Status" table on page III
"Advanced I/O"
IH
input leakage current information was added to all "Minimum and
Table 2-2 • Recommended Operating Conditions
1
Table 2-74 • 1.8 V LVCMOS High
"
RAM4K9, the following specifications were removed:
RAM512X18, the following specifications were removed:
table,
figure and pin table for A3P060 are new.
Information", and the
section was revised to add a bullet regarding wide range
Table 2 • ProASIC3 FPGAs Package Sizes
was revised to include the fact that some RoHS
R e v i s i o n 9
Table 1 • ProASIC3 Product
Changes
is new.
was updated to include a value for typical
"Temperature Grade Offerings"
1
was updated.
was revised to add definitions of
Slew, V
indicates the status for each
CCI
had a typo. It was
1,2
Family, the
were updated.
Dimensions,
table.
"I/Os
was
2-100
2-101
Page
I
3-15
2-58
N/A
N/A
N/A
N/A
N/A
1-7
1-7
2-2
2-3
2-6
–
III
I
I
IV
4 -1