A3P125-FGG144 Actel, A3P125-FGG144 Datasheet - Page 211

• Manufacturer Part Number: A3P125-FGG144
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of A3P125-FGG144

• Processor Series: A3P125
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 125 K
• Package / Case: FPBGA-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision
v2.0
(continued)
Advance v0.7
(January 2007)
Advance v0.6
(April 2006)
In EQ 3-2, 150 was changed to 110 and the result changed from 3.9 to 1.951.
Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was
updated.
Table 3-5 • Package Thermal Resistivities was updated.
Table 3-14 • Summary of Maximum and Minimum DC Input and Output Levels
Applicable to Commercial and Industrial Conditions—Software Default Settings
(Advanced) and Table 3-17 • Summary of Maximum and Minimum DC Input
Levels Applicable to Commercial and Industrial Conditions (Standard Plus) were
updated.
Table 3-20 • Summary of I/O Timing Characteristics—Software Default Settings
(Advanced) and Table 3-21 • Summary of I/O Timing Characteristics—Software
Default Settings (Standard Plus) were updated.
Table
Consumption in ProASIC3 Devices was updated.
Table 3-24 • I/O Output Buffer Maximum Resistances1 (Advanced) and Table 3-
25 • I/O Output Buffer Maximum Resistances1 (Standard Plus) were updated.
Table 3-17 • Summary of Maximum and Minimum DC Input Levels Applicable to
Commercial and Industrial Conditions was updated.
Table 3-28 • I/O Short Currents IOSH/IOSL (Advanced) and Table 3-29 • I/O
Short Currents IOSH/IOSL (Standard Plus) were updated.
The note in Table 3-32 • I/O Input Rise Time, Fall Time, and Related I/O
Reliability was updated.
Figure 3-33 • Write Access After Write onto Same Address, Figure 3-34 • Read
Access After Write onto Same Address, and Figure 3-35 • Write Access After
Read onto Same Address are new.
Figure 3-43 • Timing Diagram was updated.
Ambient was deleted from the "Speed Grade and Temperature Grade Matrix".
Notes were added to the package diagrams identifying if they were top or bottom
view.
The A3P030 "132-Pin QFN" table is new.
The A3P060 "132-Pin QFN" table is new.
The A3P125 "132-Pin QFN" table is new.
The A3P250 "132-Pin QFN" table is new.
The A3P030 "100-Pin VQFP" table is new.
In the "I/Os Per Package" table, the I/O numbers were added for A3P060,
A3P125, and A3P250. The A3P030-VQ100 I/O was changed from 79 to 77.
The term flow-through was changed to pass-through.
Table 1 was updated to include the QN132.
The "I/Os Per Package" table was updated with the QN132. The footnotes were
also updated. The A3P400-FG144 I/O count was updated.
"Automotive ProASIC3 Ordering Information" was updated with the QN132.
3-11 • Different
Components
R e v i s i o n 9
Changes
Contributing
to
Dynamic
ProASIC3 Flash Family FPGAs
Power
3-17 to 3-
3-20 to
3-22 to
3-24 to
3-82 to
Page
3-96
3-20
3-22
3-18
3-26
3-27
3-84
4-11
N/A
N/A
3-5
3-5
4-2
4-4
4-6
4-8
3-6
3-9
17
iv
iii
ii
ii
ii
4 -5