A3P125-FGG144 Actel, A3P125-FGG144 Datasheet - Page 94

• Manufacturer Part Number: A3P125-FGG144
• Description: FPGA - Field Programmable Gate Array 125K System Gates
• Manufacturer: Actel

Specifications of A3P125-FGG144

• Processor Series: A3P125
• Core: IP Core
• Maximum Operating Frequency: 350 MHz
• Number Of Programmable I/os: 133
• Data Ram Size: 36864
• Delay Time: 11.1 ns
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: A3PE-Proto-Kit, A3PE-Brd1500-Skt, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, FlashPro 4, FlashPro 3, FlashPro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 125 K
• Package / Case: FPBGA-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ProASIC3 DC and Switching Characteristics
Figure 2-20 • Input DDR Timing Diagram
Table 2-102 • Input DDR Propagation Delays
2- 80
Out_QR
Out_QF
Parameter
t
t
t
t
t
t
t
t
t
t
t
F
Note:
DDRICLKQ1
DDRICLKQ2
DDRISUD
DDRIHD
DDRICLR2Q1
DDRICLR2Q2
DDRIREMCLR
DDRIRECCLR
DDRIWCLR
DDRICKMPWH
DDRICKMPWL
DDRIMAX
Data
CLK
CLR
For specific junction temperature and voltage-supply levels, refer to
Commercial-Case Conditions: T
Timing Characteristics
Clock-to-Out Out_QR for Input DDR
Clock-to-Out Out_QF for Input DDR
Data Setup for Input DDR (Fall)
Data Setup for Input DDR (Rise)
Data Hold for Input DDR (Fall)
Data Hold for Input DDR (Rise)
Asynchronous Clear-to-Out Out_QR for Input DDR
Asynchronous Clear-to-Out Out_QF for Input DDR
Asynchronous Clear Removal time for Input DDR
Asynchronous Clear Recovery time for Input DDR
Asynchronous Clear Minimum Pulse Width for Input DDR
Clock Minimum Pulse Width High for Input DDR
Clock Minimum Pulse Width Low for Input DDR
Maximum Frequency for Input DDR
t
t
1
DDRICLR2Q1
DDRICLR2Q2
t
DDRIREMCLR
2
3
t
DDRICLKQ1
Description
J
= 70°C, Worst Case VCC = 1.425 V
4
2
R e visio n 9
3
5
t
DDRICLKQ2
t
DDRISUD
Table 2-6 on page 2-6
6
4
5
7
0.27
0.39
0.25
0.25
0.00
0.00
0.46
0.57
0.00
0.22
0.22
0.36
0.32
TBD
–2
t
DDRIHD
0.31
0.44
0.28
0.28
0.00
0.00
0.53
0.65
0.00
0.25
0.25
0.41
0.37
TBD
–1
t
for derating values.
8
DDRIRECCLR
6
7
TBD
Std.
0.37
0.52
0.33
0.33
0.00
0.00
0.62
0.76
0.00
0.30
0.30
0.48
0.43
9
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns