LFE2M20E-5FN256C Lattice, LFE2M20E-5FN256C Datasheet - Page 249

• Manufacturer Part Number: LFE2M20E-5FN256C
• Description: FPGA - Field Programmable Gate Array 19K LUTs 140 I/O SERDES DSP -5
• Manufacturer: Lattice

Specifications of LFE2M20E-5FN256C

• Number Of Macrocells: 19000
• Maximum Operating Frequency: 311 MHz
• Number Of Programmable I/os: 140
• Data Ram Size: 1246208
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LFE2M20E/SE and LFE2M35E/SE Logic Signal Connections: 484 fpBGA
Number
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
M22
M21
M16
M17
M20
M19
M18
Ball
R21
R20
R16
R18
R19
P22
P21
P16
P17
P20
P19
P18
N16
N22
N21
N17
N18
K22
K21
K16
K17
T20
T21
L16
L22
L21
L17
L18
L20
L19
-
RLM0_PLLCAP
Function
Ball/Pad
VCCIO8
GNDIO3
VCCIO3
GNDIO3
GNDIO3
VCCIO3
GNDIO3
VCCIO3
VCCIO3
GNDIO3
VCCIO3
PR48B
PR48A
PR47B
PR47A
PR45B
PR45A
PR44B
PR44A
PR43B
PR43A
PR42B
PR42A
PR41B
PR41A
PR40B
PR40A
PR39B
PR39A
PR38B
PR38A
PR37B
PR37A
PR36B
PR36A
PR35B
PR35A
PR34B
PR34A
PR32B
PR32A
PR31B
PR31A
PR30B
PR30A
PR29B
PR29A
-
Bank
LFE2M20E/SE
8
8
8
8
8
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
-
-
-
-
-
DOUT/CSON/CSSPI1N***
RLM0_GDLLC_IN_A**
RLM0_GPLLC_IN_A**
RLM0_GDLLT_IN_A**
RLM0_GPLLT_IN_A**
RLM0_GDLLC_FB_A
RLM0_GPLLC_FB_A
RLM0_GDLLT_FB_A
RLM0_GPLLT_FB_A
RLM1_SPLLC_FB_A
RLM1_SPLLT_FB_A
RLM1_SPLLC_IN_A
RLM1_SPLLT_IN_A
Dual Function
DI/CSSPI0N***
BUSY/SISPI***
D7/SPID0***
RDQS38
RDQ38
RDQ38
RDQ38
RDQ38
RDQ38
RDQ38
RDQ38
RDQ38
RDQ38
RDQ38
RDQ38
RDQ38
RDQ38
RDQ38
RDQ38
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
T
4-146
RLM0_PLLCAP
Function
Ball/Pad
GNDIO3
GNDIO3
GNDIO3
GNDIO3
GNDIO3
VCCIO8
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
VCCIO3
PR63B
PR63A
PR62B
PR62A
PR60B
PR60A
PR59B
PR59A
PR58B
PR58A
PR57B
PR57A
PR51B
PR51A
PR50B
PR50A
PR49B
PR49A
PR48B
PR48A
PR47B
PR47A
PR46B
PR46A
PR45B
PR45A
PR44B
PR44A
PR42B
PR42A
PR41B
PR41A
PR40B
PR40A
PR39B
PR39A
LatticeECP2/M Family Data Sheet
Bank
8
8
8
8
8
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
-
-
-
-
RLM0_GPLLT_FB_A/RDQS57****
LFE2M35E/SE
RLM0_GDLLC_IN_A**/RDQ57
RLM0_GPLLC_IN_A**/RDQ57
RLM0_GDLLT_IN_A**/RDQ57
RLM0_GPLLT_IN_A**/RDQ57
RLM0_GDLLC_FB_A/RDQ57
RLM0_GPLLC_FB_A/RDQ57
RLM0_GDLLT_FB_A/RDQ57
DOUT/CSON/CSSPI1N***
RLM2_SPLLC_FB_A
RLM2_SPLLT_FB_A
RLM2_SPLLC_IN_A
RLM2_SPLLT_IN_A
Dual Function
DI/CSSPI0N***
BUSY/SISPI***
D7/SPID0***
RDQS48
RDQ48
RDQ48
RDQ48
RDQ48
RDQ48
RDQ48
RDQ48
RDQ48
RDQ48
RDQ48
RDQ48
RDQ48
RDQ48
RDQ48
RDQ48
Pinout Information
Differential
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T