LFE2M20E-5FN256C Lattice, LFE2M20E-5FN256C Datasheet - Page 289

• Manufacturer Part Number: LFE2M20E-5FN256C
• Description: FPGA - Field Programmable Gate Array 19K LUTs 140 I/O SERDES DSP -5
• Manufacturer: Lattice

Specifications of LFE2M20E-5FN256C

• Number Of Macrocells: 19000
• Maximum Operating Frequency: 311 MHz
• Number Of Programmable I/os: 140
• Data Ram Size: 1246208
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LFE2M50E/SE and LFE2M70E/SE Logic Signal Connections: 900 fpBGA
Lattice Semiconductor
Number
GNDIO
GNDIO
GNDIO
VCCIO
VCCIO
VCCIO
VCCIO
Ball
AA1
AA2
AB1
AA7
AB2
AB3
AA5
AA6
AB4
W1
W5
W6
W3
W4
W2
U8
U5
U4
U3
U2
U6
U1
V9
V7
V8
V2
V5
V6
V1
Y4
Y1
Y2
Y5
Y6
Y3
Y9
Y8
Y7
-
-
-
-
Function
Ball/Pad
GNDIO6
GNDIO6
GNDIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO6
PL46B
PL48A
PL48B
PL49A
PL49B
PL50A
PL50B
PL51A
PL51B
PL52A
PL52B
PL53A
PL53B
PL54A
PL54B
PL55A
PL55B
PL57A
PL57B
PL58A
PL58B
PL59A
PL59B
PL60A
PL60B
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
-
-
-
-
LFE2M50E/SE
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
LLM3_SPLLC_FB_A
Dual Function
LDQS52
LDQ52
LDQ52
LDQ52
LDQ52
LDQ52
LDQ52
LDQ52
LDQ52
LDQ52
LDQ52
LDQ52
LDQ52
LDQ52
LDQ52
LDQ52
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
4-186
C
C
C
C
C
C
T
T
T
T
C
T
T
Function
Ball/Pad
GNDIO6
VCCIO6
GNDIO6
VCCIO6
GNDIO6
VCCIO6
GNDIO6
VCCIO6
GNDIO6
VCCIO6
PL58B
PL60A
PL60B
PL61A
PL61B
PL62A
PL62B
PL63A
PL63B
PL64A
PL64B
PL65A
PL65B
PL66A
PL66B
PL67A
PL67B
PL69A
PL69B
PL70A
PL70B
PL71A
PL71B
PL72A
PL72B
PL73A
PL73B
PL74A
PL74B
PL75A
PL75B
PL76A
PL76B
PL78A
PL78B
PL79A
PL79B
PL80A
-
LatticeECP2/M Family Data Sheet
Bank
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
-
-
-
-
-
-
LFE2M70E/SE
LLM3_SPLLC_FB_A/LDQ55
Dual Function
Pinout Information
LDQS64
LDQS73
LDQ64
LDQ64
LDQ64
LDQ64
LDQ64
LDQ64
LDQ64
LDQ64
LDQ64
LDQ64
LDQ64
LDQ64
LDQ64
LDQ64
LDQ64
LDQ73
LDQ73
LDQ73
LDQ73
LDQ73
LDQ73
LDQ73
LDQ73
LDQ73
LDQ73
LDQ73
LDQ73
LDQ73
LDQ73
LDQ73
LDQ82
LDQ82
LDQ82
LDQ82
LDQ82
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T