LFE2M20E-5FN256C Lattice, LFE2M20E-5FN256C Datasheet - Page 279

• Manufacturer Part Number: LFE2M20E-5FN256C
• Description: FPGA - Field Programmable Gate Array 19K LUTs 140 I/O SERDES DSP -5
• Manufacturer: Lattice

Specifications of LFE2M20E-5FN256C

• Number Of Macrocells: 19000
• Maximum Operating Frequency: 311 MHz
• Number Of Programmable I/os: 140
• Data Ram Size: 1246208
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LFE2M35E/SE and LFE2M50E/SE Logic Signal Connections: 672 fpBGA
Lattice Semiconductor
Number
VCCIO
GNDIO
VCCIO
Ball
H20
G26
H19
C25
C22
C21
C20
C24
C23
D19
C19
C15
C14
C18
C17
F21
F26
E24
E23
A24
B25
B24
A21
A22
B21
B20
A20
B23
A23
B19
E19
A15
B15
A18
B18
-
-
URC_SQ_VCCTX0
URC_SQ_VCCTX1
URC_SQ_REFCLK
URC_SQ_REFCLK
URC_SQ_VCCTX2
URC_SQ_HDINP0
URC_SQ_HDINN0
URC_SQ_HDINN1
URC_SQ_HDINP1
URC_SQ_HDINP2
URC_SQ_HDINN2
URC_SQ_VCCRX
URC_SQ_VCCIB0
URC_SQ_HDOUT
URC_SQ_VCCOB
URC_SQ_HDOUT
URC_SQ_HDOUT
URC_SQ_VCCOB
URC_SQ_HDOUT
URC_SQ_VCCRX
URC_SQ_VCCIB1
URC_SQ_VCCIB2
URC_SQ_VCCRX
URC_SQ_HDOUT
URC_SQ_VCCOB
URC_SQ_HDOUT
URC_SQ_VCCAU
URC_SQ_VCCP
Function
Ball/Pad
VCCIO2
GNDIO2
VCCIO4
PR12B
PR12A
PR11B
PR11A
XRES
PR9B
PR9A
X33
N0
N1
N2
P0
P1
P2
N
P
0
0
1
1
2
2
-
-
Bank
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
2
2
2
2
2
2
2
4
-
-
-
-
LFE2M35E/SE
RUM0_SPLLC_FB_A/RDQ15
RUM0_SPLLT_FB_A/RDQ15
RUM0_SPLLC_IN_A/RDQ15
RUM0_SPLLT_IN_A/RDQ15
Dual Function
VREF2_2
VREF1_2
Differential
C (LVDS)*
T (LVDS)*
4-176
C
T
C
T
T
C
T
C
C
T
C
T
C
T
T
C
T
C
URC_SQ_VCCAUX33
URC_SQ_HDOUTP0
URC_SQ_HDOUTN0
URC_SQ_HDOUTN1
URC_SQ_HDOUTP1
URC_SQ_HDOUTP2
URC_SQ_HDOUTN2
URC_SQ_REFCLKN
URC_SQ_REFCLKP
URC_SQ_VCCOB0
URC_SQ_VCCOB1
URC_SQ_VCCOB2
URC_SQ_VCCRX0
URC_SQ_VCCTX0
URC_SQ_VCCTX1
URC_SQ_VCCRX1
URC_SQ_VCCRX2
URC_SQ_VCCTX2
URC_SQ_HDINP0
URC_SQ_VCCIB0
URC_SQ_HDINN0
URC_SQ_HDINN1
URC_SQ_HDINP1
URC_SQ_HDINP2
URC_SQ_HDINN2
URC_SQ_VCCIB1
URC_SQ_VCCIB2
URC_SQ_VCCP
Function
Ball/Pad
GNDIO2
VCCIO2
GNDIO2
VCCIO2
PR12B
PR12A
PR11B
PR11A
XRES
PR9B
PR9A
-
LatticeECP2/M Family Data Sheet
Bank
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
2
2
2
2
2
2
2
2
-
-
-
-
LFE2M50E/SE
RUM0_SPLLC_FB_A
RUM0_SPLLT_FB_A
RUM0_SPLLC_IN_A
RUM0_SPLLT_IN_A
Dual Function
Pinout Information
VREF2_2
VREF1_2
Differential
C*
T*
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T