LFE2M20E-5FN256C Lattice, LFE2M20E-5FN256C Datasheet - Page 5

• Manufacturer Part Number: LFE2M20E-5FN256C
• Description: FPGA - Field Programmable Gate Array 19K LUTs 140 I/O SERDES DSP -5
• Manufacturer: Lattice

Specifications of LFE2M20E-5FN256C

• Number Of Macrocells: 19000
• Maximum Operating Frequency: 311 MHz
• Number Of Programmable I/os: 140
• Data Ram Size: 1246208
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-1. Simplified Block Diagram, ECP2-6 Device (Top Level)
sysCLOCK PLLs and DLLs
Frequency Synthesis and
Clock Alignment
Figure 2-2. Simplified Block Diagram, ECP2M20 Device (Top Level)
Configuration
Logic, Including
dual boot and encryption,
and soft-error detection
Programmable
Function Units
(PFUs)
sysDSP Blocks
Multiply and
Accumulate Support
sysMEM Block RAM
18kbit Dual Port
Flexible sysIO
Buffers:
LVCMOS, HSTL
SSTL, LVDS
Programmable
Function Units
(PFUs)
DSP Blocks
Multiply & Accumulate
Support
sysMEM Block
RAM 18kbit Dual Port
On-Chip
Oscillator
2-2
Channel
3
Channel
2
LatticeECP2/M Family Data Sheet
Channel
1
Channel
0
Flexible sysIO Buffers:
LVCMOS, HSTL, SSTL,
LVDS, and other standards
Pre-engineered source
synchronous support
• DDR1/2
• SPI4.2
• ADC/DAC devices
Flexible routing optimized
for speed, cost and routability
Configuration logic, including
dual boot and encryption.
On-chip oscillator and
soft-error detection.
Configuration port
SERDES
Pre-Engineered
Source Synchronous
Support
• DDR1/2
• SPI4.2
• ADC/DAC devices
sysCLOCK SPLLs
Flexible Routing
optimized for speed,
cost & routability
sysCLOCK GPLLs
& GDLLs
Frequency Synthesis
& Clock Alignment
Configuration Port
Architecture