LFE2M20E-5FN256C Lattice, LFE2M20E-5FN256C Datasheet - Page 386

• Manufacturer Part Number: LFE2M20E-5FN256C
• Description: FPGA - Field Programmable Gate Array 19K LUTs 140 I/O SERDES DSP -5
• Manufacturer: Lattice

Specifications of LFE2M20E-5FN256C

• Number Of Macrocells: 19000
• Maximum Operating Frequency: 311 MHz
• Number Of Programmable I/os: 140
• Data Ram Size: 1246208
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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April 2011
February 2006
August 2006
Date
Version
01.0
01.1
Pinout Information
DC and Switching
Characteristics
Introduction
Architecture
Section
—
LatticeECP2/M Family Data Sheet
Initial release.
Updated Table 1-1 “LatticeECP2 Family Selection Guide”.
Updated Figure 2-2 “PFU Diagram”.
Updated Figure 2-13 “Secondary Clock Regions ECP2-50”.
Updated Figure 2-25 “PIC Diagram”.
Updated Figure 2-26 “Input Register Block for Left, Right and Bottom
Edges”.
Updated Figure 2-28 “Output Register Block for Left, Right and Bottom
Edges”.
Updated Figure 2-30 “DQS Input Routing for Left and Right Edges”.
Updated Figure 2-32 “Edge Clock, DLL Calibration and DQS Local Bus
Distribution”.
Table 2-15 Selectable Master Clock (CCLK) Frequencies - Removed
frequencies 15, 20, 21, 22, 23, 30, 34, 41, 45, 51, 55, 60.
Replaced “CLKINDEL” with “CLKO”.
Updated SED section.
Qualified device migration capability when using DQS banks for DDR
interfaces.
Added VCCPLL to the Recommended Operating Conditions table.
Removed note 5 from “Hot Specifications” section.
Added notes 7 and 8 to “Initialization Supply” Current table.
Change note 6 - “...down to 95MHz” to “...down to 95MHz for DDR and
133MHz for DDR2” .
New “Typical Building Block Function Performance” numbers.
New External Switching Characteristics numbers.
New Internal Switching Characteristics numbers.
New Family Timing Adders numbers.
Updated Timings for GPLLs, SPLLs and DLLs.
Added sysCONFIG waveforms.
Remove HSTL15D_II from sysIO Recommended Operating Conditions
table.
Updated Supply and Initialization Currents for ECP2-50.
Added VCCPLL to the Signal Descriptions table.
Updated Logic Signal Connections tables to include 484-fpBGA for the
ECP2-50.
Added Logic Signal Connections tables for ECP2-12 devices.
Updated Pin Information Summary table to include ECP2-12.
Updated Power Supply and NC Connections table to include ECP2-12.
Added note 2 to DDR Strobe (DQS) Pin table.
Added Information on: PCI, DDR & SPI4.2 Capabilities of the device-
Package combination.
7-1
Change Summary
Revision History
DS1006 Revision History
Data Sheet DS1006