LFE2M20E-5FN256C Lattice, LFE2M20E-5FN256C Datasheet - Page 342

• Manufacturer Part Number: LFE2M20E-5FN256C
• Description: FPGA - Field Programmable Gate Array 19K LUTs 140 I/O SERDES DSP -5
• Manufacturer: Lattice

Specifications of LFE2M20E-5FN256C

• Number Of Macrocells: 19000
• Maximum Operating Frequency: 311 MHz
• Number Of Programmable I/os: 140
• Data Ram Size: 1246208
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LFE2M70E/SE and LFE2M100E/SE Logic Signal Connections: 1152 fpBGA
Lattice Semiconductor
Number
GNDIO
GNDIO
GNDIO
GNDIO
VCCIO
VCCIO
VCCIO
AM34
AM32
AM33
AP31
AN31
AP32
AP33
AN32
AN34
AN33
AH28
AD24
AE25
AK31
AE24
AD25
AG29
AG28
AG30
AH29
AH30
AE26
AG27
AK32
AK33
AD26
AK34
AH33
AH34
AJ29
AF25
AJ28
AJ30
AF26
AJ31
AF27
AF28
AJ32
AJ33
AJ34
Ball
LRC_SQ_HDOUTN1
LRC_SQ_HDOUTN0
LRC_SQ_HDOUTP0
LRC_SQ_VCCOB0
LRC_SQ_VCCRX0
LRC_SQ_VCCTX1
LRC_SQ_VCCTX0
LRC_SQ_HDINN0
LRC_SQ_HDINP0
LRC_SQ_VCCIB0
D0/SPIFASTN***
RLM0_PLLCAP
DI/CSSPI0N***
BUSY/SISPI***
DOUT/CSON/
PROGRAMN
D7/SPID0***
CSSPI1N***
WRITEN***
Function
Ball/Pad
GNDIO8
CS1N***
GNDIO8
GNDIO3
GNDIO3
VCCIO8
VCCIO8
VCCIO3
CSN***
PR85B
PR85A
PR84B
PR84A
PR83B
PR83A
PR82B
PR82A
DONE
CFG2
CFG1
CFG0
CCLK
INITN
D1***
D2***
D3***
D4***
D5***
D6***
LFE2M70E/SE
Bank
13
13
13
13
13
13
13
13
13
13
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3
3
3
3
3
3
3
3
3
3
-
-
-
-
RLM0_GPLLT_FB_A/RDQS82****
RLM0_GDLLC_IN_A**
RLM0_GPLLC_IN_A**
RLM0_GDLLT_IN_A**
RLM0_GPLLT_IN_A**
RLM0_GDLLC_FB_A
RLM0_GPLLC_FB_A
RLM0_GDLLT_FB_A
Dual Function
Differential
C (LVDS)*
T (LVDS)*
C (LVDS)*
T (LVDS)*
4-239
C
C
C
C
C
T
T
T
T
LRC_SQ_HDOUTN1
LRC_SQ_HDOUTN0
LRC_SQ_HDOUTP0
LRC_SQ_VCCOB0
LRC_SQ_VCCRX0
LRC_SQ_VCCTX1
LRC_SQ_VCCTX0
LRC_SQ_HDINN0
LRC_SQ_HDINP0
LRC_SQ_VCCIB0
D0/SPIFASTN***
RLM0_PLLCAP
DI/CSSPI0N***
BUSY/SISPI***
DOUT/CSON/
PROGRAMN
D7/SPID0***
CSSPI1N***
WRITEN***
Function
Ball/Pad
GNDIO8
CS1N***
GNDIO8
GNDIO3
PR102A
PR101A
PR100B
GNDIO3
VCCIO8
VCCIO8
PR102B
PR101B
VCCIO3
PR100A
CSN***
PR99B
PR99A
DONE
CFG2
CFG1
CFG0
CCLK
INITN
D1***
D2***
D3***
D4***
D5***
D6***
LatticeECP2/M Family Data Sheet
LFE2M100E/SE
Bank
13
13
13
13
13
13
13
13
13
13
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3
3
3
3
3
3
3
3
8
8
8
8
3
3
-
-
-
-
RLM0_GDLLC_FB_A/RDQ99
RLM0_GPLLC_FB_A/RDQ99
RLM0_GDLLT_FB_A/RDQ99
RLM0_GDLLC_IN_A**/
RLM0_GPLLC_IN_A**/
RLM0_GDLLT_IN_A**/
RLM0_GPLLT_IN_A**/
RLM0_GPLLT_FB_A/
Dual Function
Pinout Information
RDQS99
RDQ99
RDQ99
RDQ99
RDQ99
Differential
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
T
T
T
T