SCC68692C1A44 NXP Semiconductors, SCC68692C1A44 Datasheet - Page 24

• Manufacturer Part Number: SCC68692C1A44
• Description: UART, DUAL, SMD, 68692C1, PLCC44
• Manufacturer: NXP Semiconductors

Specifications of SCC68692C1A44

• No. Of Channels: 2
• Uart Features: Quadruple Buffered Receiver Data Register
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Data Rate: 115.2Kilobaud
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
controlled by the receiver and the transmitter at the same time is
allowed, but would usually be incompatible.
RTS can also be controlled by the commands 1000 and 1001 in the
command register. RTS is expressed at the MP0 pin which is still an
output port. Therefore, the state of MP0 should be set LOW (either
by commands of the CR register or by writing to the Set Output
Ports Register) for the receiver to generate the proper RTS signal.
The logic at the output is basically a NAND of the MP0 bit register
and the RTS signal as generated by the receiver. When the RTS
flow control is selected via the MR(7) bit the state of the MP0
register is not changed. Terminating the use of “Flow Control” (via
the MR registers) will return the MP0 pin to the control of the MP0
register.
Transmitter Disable Note
The sequence of instructions enable transmitter — load transmit
holding register — disable transmitter will result in nothing being
sent if the time between the end of loading the transmit holding
register and the disable command is less that 3/16 bit time in the
16x mode or one bit time in the 1x mode. Also, if the transmitter,
while in the enabled state and underrun condition, is immediately
disabled after a single character is loaded to the transmit holding
register, that character will not be sent.
In general, when it is desired to disable the transmitter before the
last character is sent AND the TxEMT bit is set in the status register
(TxEMT is always set if the transmitter has underrun or has just
been enabled), be sure the TxRDY bit is active immediately before
issuing the transmitter disable instruction. TxRDY sets at the end of
the “start bit” time. It is during the start bit that the data in the
transmit holding register is transferred to the transmit shift register.
Non-standard baud rates are available as shown in Table 6 below,
via the BRG Test function.
2004 Mar 03
Dual asynchronous receiver/transmitter (DUART)
Reset can also be accomplished easily by first exiting the wake-up mode (MR1[4:3] = 00 or 01 or 10), then issuing a receiver software or
Receiver Reset in the Normal Mode (Receiver Enabled)
Reset can be accomplished easily by issuing a receiver software or hardware reset followed by a receiver enable. All receiver data,
status and programming will be preserved and available before reset. The reset will NOT affect the programming.
Receiver Reset in the Wake-Up Mode (MR1[4:3] = 11)
hardware reset followed by a wake-up re-entry (MR1[4:3] = 11). All receiver data, status and programming will be preserved and
available before reset. The reset will NOT affect other programming.
The reason for this is the receiver is partially enabled when the parity bits are at ‘11’. Thus the receiver disable and reset is bypassed by
the partial enabling of the receiver.
24
When in the BRG test mode, the baud rates change as shown to the
The test mode at address H‘2’ changes all transmitters and
receivers to the 1x mode and connects the output ports to some
internal nodes.
Table 6. Baud Rate
NOTE:
Each read on address H‘A’ will toggle the baud rate test mode.
left. This change affects all receivers and transmitters on the
DUART. See “Extended baud rates for SCN2681, SCN68681,
SCC2691, SCC2692, SCC68681 and SCC2698B” in application
notes elsewhere in this publication
CSR[7:4]
0000
0001
0010
0011
0100
0101
0110
1000
1001
1010
1011
1100
1101
0111
1110
1111
ACR[7] = 0
I/O2 – 16X
I/O2 – 1X
38.4K
134.5
1,200
1,050
2,400
4,800
7,200
9,600
Timer
110
200
300
600
50
Normal BRG
ACR[7] = 1
I/O2 – 16X
I/O2 – 1X
19.2K
134.5
1,200
2,000
2,400
4,800
1,800
9,600
Timer
150
300
600
110
75
ACR[7] = 0
I/O2 – 16X
I/O2 – 1X
115.2K
4,800
1,076
19.2K
28.8K
57.6K
1,050
57.6K
4,800
57.6K
9,600
38.4K
Timer
880
SCC68692
BRG Test
ACR[7] = 1
Product data
I/O2 – 16X
I/O2 – 1X
115.2K
SD00097
14.4K
28.8K
57.6K
57.6K
14.4K
19.2K
Timer
7,200
1,076
2,000
4,800
9,600
880