SCC68692C1A44 NXP Semiconductors, SCC68692C1A44 Datasheet - Page 8

• Manufacturer Part Number: SCC68692C1A44
• Description: UART, DUAL, SMD, 68692C1, PLCC44
• Manufacturer: NXP Semiconductors

Specifications of SCC68692C1A44

• No. Of Channels: 2
• Uart Features: Quadruple Buffered Receiver Data Register
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Data Rate: 115.2Kilobaud
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

3. Typical values are at +25 C, typical supply voltages, and typical processing parameters.
4. Test conditions for outputs: C
5. This specification will impose maximum 68000 CPU CLK to 6 MHz. Higher CPU CLK can be used if repeating bus reads are not performed.
6. This specification imposes a lower bound on CSN and IACKN LOW, guaranteeing that it will be LOW for at least 1 CLK period. This require-
7. This specification is made only to insure that DTACKN is asserted with respect to the rising edge of the X1/CLK pin as shown in the timing
8. Guaranteed by characterization of sample units.
9. Minimum frequencies are not tested but are guaranteed by design.
10. 325 ns maximum for T
11. Operation to 0 MHz is assured by design. Minimum test frequency is 2.0 MHz.
12. See UART application note for power-down currents less than 5 A.
communications Channels A and B, input port and output port. Refer
allow read and write operations to take place between the controlling
determine all currently active interrupting conditions. When IACKN is
X1/CLK. The clock serves as the basic timing reference for the Baud
Philips Semiconductors
BLOCK DIAGRAM
The SCC68692 DUART consists of the following eight major
sections: data bus buffer, operation control, interrupt control, timing,
to the Block Diagram (Figure 2).
Data Bus Buffer
The data bus buffer provides the interface between the external and
internal data buses. It is controlled by the operation control block to
CPU and the DUART.
Operation Control
The operation control logic receives operation commands from the
CPU and generates appropriate signals to internal sections to
control device operation. It contains address decoding and read and
write circuits to permit communications with the microprocessor via
the data bus buffer. The DTACKN output is asserted during write
and read cycles to indicate to the CPU that data has been latched
on a write cycle, or that valid data is present on the bus on a read
cycle.
Interrupt Control
A single active-LOW interrupt output (INTRN) is provided which is
activated upon the occurrence of any of eight internal events.
Associated with the interrupt system are the Interrupt Mask Register
(IMR) and the Interrupt Status Register (ISR), the Auxiliary Control
Register (ACR), and the Interrupt Vector Register (IVR). The IMR
may be programmed to select only certain conditions to cause
INTRN to be asserted. The ISR can be read by the CPU to
asserted, and the DUART has an interrupt pending, the DUART
responds by placing the contents of the IVR register on the data bus
and asserting DTACKN.
Outputs OP3–OP7 can be programmed to provide discrete interrupt
outputs for the transmitter, receivers, and counter/timer.
TIMING CIRCUITS
Crystal Clock
The timing block consists of a crystal oscillator, a baud rate
generator, a programmable 16-bit counter/timer, and four clock
selectors. The crystal oscillator operates directly from a crystal
connected across the X1/CLK and X2 inputs. If an external clock of
the appropriate frequency is available, it may be connected to
Rate Generator (BRG), the counter/timer, and other internal circuits.
A clock signal within the limits specified in the specifications section
of this data sheet must always be supplied to the DUART.
2004 Mar 03
Dual asynchronous receiver/transmitter (DUART)
Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
ment is made on CSN only to insure assertion of DTACKN and not to guarantee operation of the part.
diagram, not to guarantee operation of the part. If the set-up time is violated, DTACKN may be asserted as shown, or may be asserted one
clock cycle later.
amb
> 70 C.
L
= 150 pF, except interrupt outputs. Test condition for interrupt outputs: C
8
full-duplex asynchronous receiver/transmitter (UART). The operating
If an external is used instead of a crystal, X1 should be driven using
a configuration similar to the one in Figure 9.
BRG
The baud rate generator operates from the oscillator or external
clock input and is capable of generating 18 commonly used data
communications baud rates ranging from 50 to 38.4 K baud. A
3.6864 MHz crystal or external clock must be used to get the
standard baud rate. The clock outputs from the BRG are at 16X the
actual baud rate. The counter/timer can be used as a timer to
produce a 16X clock for any other baud rate by counting down the
crystal clock or an external clock. The four clock selectors allow the
independent selection, for each receiver and transmitter, of any of
these baud rates or external timing signal.
Counter/Timer (C/T)
The counter timer is a 16-bit programmable divider that operates
one of three modes: Counter, Timer or Time Out mode. In all three
modes it uses the 16-bit value loaded to the CTUR and CTLR
registers. (Counter timer upper and lower preset registers).
The counter operates as a down counter and sets its output bit in
the ISR (Interrupt Status Register) each time it passes through ‘0’.
The output of the counter/timer may be seen on one of the OP pins
or as an Rx or Tx clock.
The Timer/Counter is controlled with six (6) “commands”; Start C/T,
Stop C/T, write C/T, preset registers, read C/T value, set or reset
time out mode.
Please see the detail of the commands under the Counter/Timer
register descriptions.
Communications Channels A and B
Each communications channel of the SCC68692 comprises a
frequency for each receiver and transmitter can be selected
independently from the baud rate generator, the counter timer, or
from an external input.
The transmitter accepts parallel data from the CPU, converts it to a
serial bit stream, inserts the appropriate start, stop, and optional
parity bits and outputs a composite serial stream of data on the TxD
output pin. The receiver accepts serial data on the RxD pin,
converts this serial input to parallel format, checks for start bit, stop
bit, parity bit (if any), or break condition and sends an assembled
character to the CPU.
In the Timer mode it generates a square wave.
In the Counter mode it generates a time delay.
In the Time Out mode it monitors the receiver data flow and
signals data flow has paused. In the Time Out mode the receiver
controls the starting/stopping of the C/T.
L
= 50 pF, R
L
= 2.7 k to V
SCC68692
Product data
CC
.