SCC68692C1A44 NXP Semiconductors, SCC68692C1A44 Datasheet - Page 5

• Manufacturer Part Number: SCC68692C1A44
• Description: UART, DUAL, SMD, 68692C1, PLCC44
• Manufacturer: NXP Semiconductors

Specifications of SCC68692C1A44

• No. Of Channels: 2
• Uart Features: Quadruple Buffered Receiver Data Register
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: PLCC
• No. Of Pins: 44
• Data Rate: 115.2Kilobaud
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
PIN DESCRIPTION
2004 Mar 03
SYMBOL
D0–D7
CSN
R/WN
A1–A4
RESETN
DTACKN
INTRN
IACKN
X1/CLK
X2
RxDA
RxDB
TxDA
TxDB
OP0
OP1
OP2
OP3
OP4
OP5
OP6
OP7
IP0
IP1
IP2
IP3
IP4
IP5
V
GND
Dual asynchronous receiver/transmitter (DUART)
CC
25,16,24,17
23,18,22,19
PIN NO.
1,2,5,6
35
34
21
37
32
33
31
10
30
11
29
12
28
13
27
14
26
15
36
39
38
40
20
8
9
7
4
2
TYPE
I/O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Output 3: General purpose output or open-drain, active-LOW counter/timer output or Channel B transmitter
Input 2: General purpose input or Channel B receiver external clock input (RxCB), or counter/timer external
Data Bus: Bidirectional 3-State data bus used to transfer commands, data and status between the DUART
and the CPU. D0 is the least significant bit.
Chip Enable: Active-LOW input signal. When LOW, data transfers between the CPU and the DUART are
enabled on D0–D7 as controlled by the R/WN and A1–A4 inputs. When CEN is HIGH, the DUART places
the D0–D7 lines in the 3-State condition.
Read/Write: A HIGH input indicates a read cycle and a LOW input indicates a write cycle, when a cycle is
initiated by assertion of the CSN input.
Address Inputs: Select the DUART internal registers and ports for read/write operations.
Reset: A LOW level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), initializes the IVR to hex
0F, puts OP0–OP7 in the HIGH state, stops the counter/timer, and puts Channels A and B in the inactive
state, with the TxDA and TxDB outputs in the mark (HIGH) state. Resets Test Mode, sets MR pointer to MR1.
Data Transfer Acknowledge: 3-State active-LOW output asserted in write, read, or interrupt cycles to
indicate proper transfer of data between the CPU and the DUART.
Interrupt Request: Active-LOW, open-drain output which signals the CPU that one or more of the eight
maskable interrupting conditions are true.
Interrupt Acknowledge: Active-LOW input indicating an interrupt acknowledge cycle. In response, the
DUART will place the interrupt vector on the data bus and will assert DTACKN if it has an interrupt pending.
Crystal 1: Crystal connection or an external clock input. A crystal of a clock the appropriate frequency
(nominally 3.6864 MHz) must be supplied at all times. For crystal connections see Figure 9, Clock Timing.
Crystal 2: Crystal connection. See Figure 9. If a crystal is not used it is best to keep this pin not connected
although it is permissible to ground it.
Channel A Receiver Serial Data Input: The least significant bit is received first. “Mark” is HIGH, “space” is LOW.
Channel B Receive Serial Data Input: The least significant bit is received first. “Mark” is HIGH, “space” is LOW.
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held
in the “mark” condition when the transmitter is disabled, idle or when operating in local loopback mode.
“Mark” is HIGH, “space” is LOW.
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This output is held
in the ‘mark’ condition when the transmitter is disabled, idle, or when operating in local loopback mode.
‘Mark’ is HIGH, ‘space’ is LOW.
Output 0: General purpose output or Channel A request to send (RTSAN, active-LOW). Can be
deactivated automatically on receive or transmit.
Output 1: General purpose output or Channel B request to send (RTSBN, active-LOW). Can be
deactivated automatically on receive or transmit.
Output 2: General purpose output, or Channel A transmitter 1X or 16X clock output, or Channel A receiver
1X clock output.
1X clock output, or Channel B receiver 1X clock output.
Output 4: General purpose output or Channel A open-drain, active-LOW, RxRDYAN/FFULLAN output.
Output 5: General purpose output or Channel B open-drain, active-LOW, RxRDYBN/FFULLBN output.
Output 6: General purpose output or Channel A open-drain, active-LOW, TxRDYAN output.
Output 7: General purpose output or Channel B open-drain, active-LOW, TxRDYBN output.
Input 0: General purpose input or Channel A clear to send active-LOW input (CTSAN). Pin has an internal
V
Input 1: General purpose input or Channel B clear to send active-LOW input (CTSBN). Pin has an internal
V
clock input. When external clock is used by the receiver, the received data is sampled on the rising edge of
the clock. Pin has an internal V
Input 3: General purpose input or Channel A transmitter external clock input (TxCA). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an
internal V
Input 4: General purpose input or Channel A receiver external clock input (RxCA). When the external clock
is used by the receiver, the received data is sampled on the rising edge of the clock. Pin has an internal
V
Input 5: General purpose input or Channel B transmitter external clock input (TxCB). When the external
clock is used by the transmitter, the transmitted data is clocked on the falling edge of the clock. Pin has an
internal V
Power Supply: +5 V supply input.
Ground
CC
CC
CC
pull-up device supplying 1 to 4 A of current.
pull-up device supplying 1 to 4 A of current.
pull-up device supplying 1 to 4 A of current.
CC
CC
pull-up device supplying 1 to 4 A of current.
pull-up device supplying 1 to 4 A of current.
CC
pull-up device supplying 1 to 4 A of current.
5
NAME AND FUNCTION
SCC68692
Product data