LFXP2-8E-5QN208C | |
|---|---|
| Manufacturer Part Number | LFXP2-8E-5QN208C |
| Description | IC, LATTICEXP2 FPGA, 435MHZ, QFP-208 |
| Manufacturer | LATTICE SEMICONDUCTOR |
| Series | LatticeXP2 |
| LFXP2-8E-5QN208C datasheets |
|
Availability: By request
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Warranty: 60 days
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Specifications of LFXP2-8E-5QN208C | |||
|---|---|---|---|
| No. Of Logic Blocks | 8000 | No. Of Macrocells | 4000 |
| Family Type | LatticeXP2 | No. Of Speed Grades | 5 |
| No. Of I/o's | 146 | Clock Management | PLL |
| Total Ram Bits | 221Kbit | Lead Free Status / RoHS Status | Lead free / RoHS Compliant |
PrevNext
Lattice Semiconductor
Figure 2-28. DQS Input Routing (Left and Right)
DQS
Figure 2-29. DQS Input Routing (Top and Bottom)
DQS
LatticeXP2 Family Data Sheet
PADA "T"
PIO A
LVDS Pair
PADB "C"
PIO B
PADA "T"
PIO A
LVDS Pair
PADB "C"
PIO B
PADA "T"
PIO A
LVDS Pair
PADB "C"
PIO B
PADA "T"
PIO A
LVDS Pair
PADB "C"
PIO B
sysIO
Assigned
PIO A
DQS Pin
Buffer
PADA "T"
Delay
LVDS Pair
PADB "C"
PIO B
PADA "T"
PIO A
LVDS Pair
PADB "C"
PIO B
PADA "T"
PIO A
LVDS Pair
PIO B
PADB "C"
PIO A
PADA "T"
LVDS Pair
PIO B
PADB "C"
PADA "T"
PIO A
LVDS Pair
PADB "C"
PIO B
PADA "T"
PIO A
LVDS Pair
PADB "C"
PIO B
PADA "T"
PIO A
LVDS Pair
PADB "C"
PIO B
PADA "T"
PIO A
LVDS Pair
PADB "C"
PIO B
sysIO
Assigned
PIO A
DQS Pin
Buffer
PADA "T"
Delay
LVDS Pair
PADB "C"
PIO B
PADA "T"
PIO A
LVDS Pair
PADB "C"
PIO B
PADA "T"
PIO A
LVDS Pair
PIO B
PADB "C"
PADA "T"
PIO A
LVDS Pair
PIO B
PADB "C"
PADA "T"
PIO A
LVDS Pair
PADB "C"
PIO B
2-31
Architecture
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