IC, LATTICEXP2 FPGA, 435MHZ, QFP-208

 

LFXP2-8E-5QN208C

Manufacturer Part NumberLFXP2-8E-5QN208C
DescriptionIC, LATTICEXP2 FPGA, 435MHZ, QFP-208
ManufacturerLATTICE SEMICONDUCTOR
SeriesLatticeXP2
LFXP2-8E-5QN208C datasheets

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Specifications of LFXP2-8E-5QN208C

No. Of Logic Blocks8000No. Of Macrocells4000
Family TypeLatticeXP2No. Of Speed Grades5
No. Of I/o's146Clock ManagementPLL
Total Ram Bits221KbitLead Free Status / RoHS StatusLead free / RoHS Compliant
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Lattice Semiconductor
and loaded directly onto test nodes, or test data to be captured and shifted out for verification. The test access port
consists of dedicated I/Os: TDI, TDO, TCK and TMS. The test access port has its own supply voltage V
operate with LVCMOS3.3, 2.5, 1.8, 1.5 and 1.2 standards. For more information, please see TN1141, LatticeXP2
sysCONFIG Usage Guide.
flexiFLASH Device Configuration
The LatticeXP2 devices combine Flash and SRAM on a single chip to provide users with flexibility in device pro-
gramming and configuration. Figure 2-33 provides an overview of the arrangement of Flash and SRAM configura-
tion cells within the device. The remainder of this section provides an overview of these capabilities. See TN1141,
LatticeXP2 sysCONFIG Usage Guide, for a more detailed description.
Figure 2-33. Overview of Flash and SRAM Configuration Cells Within LatticeXP2 Devices
At power-up, or on user command, data is transferred from the on-chip Flash memory to the SRAM configuration
cells that control the operation of the device. This is done with massively parallel buses enabling the parts to oper-
ate within microseconds of the power supplies reaching valid levels; this capability is referred to as Instant-On.
The on-chip Flash enables a single-chip solution eliminating the need for external boot memory. This Flash can be
programmed through either the JTAG or Slave SPI ports of the device. The SRAM configuration space can also be
infinitely reconfigured through the JTAG and Master SPI ports. The JTAG port is IEEE 1149.1 and IEEE 1532 com-
pliant.
As described in the EBR section of the data sheet, the FlashBAK capability of the parts enables the contents of the
EBR blocks to be written back into the Flash storage area without erasing or reprogramming other aspects of the
device configuration. Serial TAG memory is also available to allow the storage of small amounts of data such as
calibration coefficients and error codes.
For applications where security is important, the lack of an external bitstream provides a solution that is inherently
more secure than SRAM only FPGAs. This is further enhanced by device locking. The device can be in one of three
modes:
EBR Blocks
SRAM
Configuration
Bits
EBR Blocks
Decryption
and Device
Lock
2-38
Architecture
LatticeXP2 Family Data Sheet
Massively Parallel
Data Transfer
Instant-ON
Flash for
Single-Chip
Solution
FlashBAK
for EBR
Storage
Device Lock
for Design
TAG
Security
Memory
SPI and JTAG
and can
CCJ

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