S25FL016K0XMFI041 Spansion Inc., S25FL016K0XMFI041 Datasheet - Page 27

• Manufacturer Part Number: S25FL016K0XMFI041
• Description: MEMORY, FLASH, 16M, 3V, SPI, 8SOIC
• Manufacturer: Spansion Inc.

Specifications of S25FL016K0XMFI041

• Memory Size: 16Mbit
• Clock Frequency: 104MHz
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: SO
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Interface: SPI
• Memory Type: RoHS Compliant
• Memory Configuration: 8K X 256 Bytes
• Interface Type: SPI
• Rohs Compliant: Yes

7.10
September 8, 2010 S25FL016K_00_02
Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO pins,
IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input the
Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for code execution (XIP)
directly from the Dual SPI in some applications.
Fast Read Dual I/O with “Continuous Read Mode”
The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the “Continuous
Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in
(M7-4) controls the length of the next Fast Read Dual I/O instruction through the inclusion or exclusion of the
first byte instruction code. The lower nibble bits of the (M3-0) are don’t care (“x”). However, the IO pins should
be high-impedance prior to the falling edge of the first data out clock.
If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after CS# is
raised and then lowered) does not require the BBh instruction code, as shown in
the instruction sequence by eight clocks and allows the Read address to be immediately entered after CS# is
asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the next instruction (after CS# is
raised and then lowered) requires the first byte instruction code, thus returning to normal operation. A
“Continuous Read Mode” Reset instruction can also be used to reset (M7-0) before issuing normal
instructions (see
CLK
CS#
IO1
IO0
CLK
CS#
IO1
IO0
Figure 7.10 Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4  10)
Mode 3
Mode 0
23 24 25
7
6
D a t a
Byte 1
5
4
0
IO Switches from Input to Output
See Continuous Read Mode Reset (FFh or FFFFh) on page
3
2
26 27
1
0
S h e e t
1
Instruction (BBh)
2
7
6
28 29 30
3
Byte 2
5
4
4
3
2
( P r e l i m i n a r y )
5
0
1
31 32
6
S25FL016K
7
6
7
5
Byte 3
4
33 34 35 36
6
7
8
3
2
4
5
A23-16
9
0
1
2
3
10
7
6
0
1
11 12 13 14 15 16
5
Byte 4
4
37 38 39
7
6
2
3
A15-8
5
4
0
1
2
3
6
0
1
Figure
7
6
5
4
17 18 19
A7-0
36.).
7.10. The upper nibble of the
3
2
Figure
0
1
7
6
M7-0
7.11. This reduces
20 21 22
5
4
23
27