LPC2220FBD144 NXP Semiconductors, LPC2220FBD144 Datasheet
LPC2220FBD144
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LPC2210/2220 16/32-bit ARM microcontrollers; flashless, with 10-bit ADC and external memory interface Rev. 06 — 11 December 2008 1. General description The LPC2210/2220 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support. For critical ...
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... N CPU operating voltage range of 1. 1. I/O power supply range of 3 3.6 V (3.3 V 16/32-bit ARM7TDMI-S processor. 3. Ordering information Table 1. Type number LPC2210FBD144 LPC2210FBD144/01 LQFP144 LPC2220FBD144 LPC2220FET144 LPC2220FET144/G LPC2210_2220_6 Product data sheet Ordering information Package Name Description LQFP144 plastic low profile quad flat package; 144 leads ...
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... NXP Semiconductors 3.1 Ordering options Table 2. Type number LPC2210FBD144 LPC2210FBD144/01 LPC2220FBD144 LPC2220FET144 LPC2220FET144/G LPC2210_2220_6 Product data sheet Ordering options RAM Rev. 06 — 11 December 2008 LPC2210/2220 16/32-bit ARM microcontrollers Fast GPIO/ Temperature range SSP/ Enhanced UART, ADC, Timer +85 C yes +85 C yes ...
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... NXP Semiconductors 4. Block diagram LPC2210 LPC2210/01 LPC2220 P0 FAST GENERAL PURPOSE I/O P1 ARM7 local bus INTERNAL SRAM CONTROLLER 16/64 kB SRAM EXTERNAL EINT[3:0] INTERRUPTS 4 CAP0 CAPTURE/ 4 CAP1 COMPARE 4 MAT0 TIMER 0/TIMER 1 4 MAT1 AIN[7:0] A/D CONVERTER P0 P1 GENERAL P2 PURPOSE I/O P3 PWM[6:1] PWM0 (1) When test/debug interface is used, GPIO/other functions sharing these pins are not available. ...
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... NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. Pin configuration for LQFP144 Fig 3. Ball configuration diagram for TFBGA144 LPC2210_2220_6 Product data sheet 1 LPC2210FBD144 LPC2210FBD144/01 LPC2220FBD144 36 ball A1 LPC2220FET144 index area Transparent top view Rev. 06 — 11 December 2008 LPC2210/2220 16/32-bit ARM microcontrollers ...
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Table 3. Ball allocation Row Column P2.22/ V P1.28/ P2.21/ DDA(1V8) D22 TDI D21 B V P1.27/ XTAL2 V DD(3V3) SSA(PLL) TDO C P0.21/ V XTAL1 V SS SSA PWM5/ CAP1.3 D P0.24 P1.19/ P0.23 ...
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Table 3. Ball allocation …continued Row Column P0.29/ P0.30/ P1.16/ P0.0/ AIN2/ AIN3/ TRACEP TXD0/ CAP0.3/ EINT3/ KT0 PWM1 MAT0.3 CAP0.0 M P3.25/ P3.24/ V P1.31/ DD(3V3) CS2 CS3 TRST P3.23/ P3.21/ ...
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... NXP Semiconductors 5.2 Pin description Table 4. Pin description Symbol Pin (LQFP) P0.0 to P0.31 [1] P0.0/TXD0/ 42 PWM1 [2] P0.1/RXD0/ 49 PWM3/EINT0 [3] P0.2/SCL/ 50 CAP0.0 [3] P0.3/SDA/ 58 MAT0.0/EINT1 [1] P0.4/SCK0/ 59 CAP0.1 [1] P0.5/MISO0/ 61 MAT0.1 [1] P0.6/MOSI0/ 68 CAP0.2 [2] P0.7/SSEL0/ 69 PWM2/EINT2 [1] P0.8/TXD1/ 75 PWM4 [2] P0.9/RXD1/ 76 PWM6/EINT3 [1] P0.10/RTS1/ 78 CAP1.0 [1] P0.11/CTS1/ 83 CAP1.1 [1] P0.12/DSR1/ 84 MAT1.0 LPC2210_2220_6 Product data sheet ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin (LQFP) [1] P0.13/DTR1/ 85 MAT1.1 [2] P0.14/DCD1/ 92 EINT1 [2] P0.15/RI1/ 99 EINT2 [2] P0.16/EINT0/ 100 MAT0.2/CAP0.2 [1] P0.17/CAP1.2/ 101 SCK1/MAT1.2 [1] P0.18/CAP1.3/ 121 MISO1/MAT1.3 [1] P0.19/MAT1.2/ 122 MOSI1/CAP1.2 [2] P0.20/MAT1.3/ 123 SSEL1/ EINT3 [1] P0.21/PWM5/ 4 CAP1.3 [1] P0.22/CAP0.0/ 5 MAT0.0 [1] P0.23 6 [1] P0.24 8 [1] P0.25 21 [4] P0 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin (LQFP) [4] P0.28/AIN1/ 25 CAP0.2/MAT0.2 [4] P0.29/AIN2/ 32 CAP0.3/MAT0.3 [4] P0.30/AIN3/ 33 EINT3/CAP0.0 P1.0 to P1.31 [5] P1.0/CS0 91 [5] P1.1/OE 90 [5] P1.16/ 34 TRACEPKT0 [5] P1.17/ 24 TRACEPKT1 [5] P1.18/ 15 TRACEPKT2 [5] P1.19/ 7 TRACEPKT3 [5] P1.20/ 102 TRACESYNC [5] P1.21/ 95 PIPESTAT0 [5] P1.22/ 86 PIPESTAT1 [5] P1.23/ 82 PIPESTAT2 [5] P1.24/ 70 TRACECLK [5] P1.25/EXTIN0 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin (LQFP) [5] P1.26/RTCK 52 [5] P1.27/TDO 144 [5] P1.28/TDI 140 [5] P1.29/TCK 126 [5] P1.30/TMS 113 [5] P1.31/TRST 43 P2.0 to P2.31 [5] P2.0/D0 98 [5] P2.1/D1 105 [5] P2.2/D2 106 [5] P2.3/D3 108 [5] P2.4/D4 109 [5] P2.5/D5 114 [5] P2.6/D6 115 [5] P2.7/D7 116 [5] P2.8/D8 117 [5] P2.9/D9 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin (LQFP) [5] P2.26/D26/ 13 BOOT0 [5] P2.27/D27/ 16 BOOT1 [5] P2.28/D28 17 [5] P2.29/D29 18 [2] P2.30/D30/ 19 AIN4 [2] P2.31/D31/ 20 AIN5 P3.0 to P3.31 [5] P3.0/A0 89 [5] P3.1/A1 88 [5] P3.2/A2 87 [5] P3.3/A3 81 [5] P3.4/A4 80 [5] P3.5/A5 74 [5] P3.6/A6 73 [5] P3.7/A7 72 [5] P3.8/A8 71 [5] P3 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin (LQFP) [5] P3.19/A19 46 [5] P3.20/A20 45 [5] P3.21/A21 44 [5] P3.22/A22 41 [5] P3.23/A23/ 40 XCLK [5] P3.24/CS3 36 [5] P3.25/CS2 35 [5] P3.26/CS1 30 [5] P3.27/WE 29 [2] P3.28/BLS3/ 28 AIN7 [4] P3.29/BLS2/ 27 AIN6 [4] P3.30/BLS1 97 [4] P3.31/BLS0 96 [5] n.c. 22 [6] RESET 135 [7] XTAL1 142 ...
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... NXP Semiconductors Table 4. Pin description …continued Symbol Pin (LQFP) V 143 DDA(1V8 31, 39, 51, DD(3V3) 57, 77, 94, 104, 112, 119 V 14 DDA(3V3) [ tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. [ tolerant pad providing digital I/O functions with TTL levels and hysteresis and 10 ns slew rate control. If configured for an input function, this pad utilizes built-in glitch fi ...
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... NXP Semiconductors 6. Functional description 6.1 Architectural overview The ARM7TDMI general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on RISC principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed CISC. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core ...
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... NXP Semiconductors Fig 4. LPC2210/2220 memory map 6.4 Interrupt controller The VIC accepts all of the interrupt request inputs and categorizes them as Fast Interrupt Request (FIQ), vectored Interrupt Request (IRQ), and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted ...
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... NXP Semiconductors Non-vectored IRQs have the lowest priority. The VIC combines the requests from all the vectored and non-vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping there. If any of the vectored IRQs are requesting, the ...
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... NXP Semiconductors 6.5 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled ...
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... NXP Semiconductors Table 7. PINSEL0 11:10 13:12 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 LPC2210_2220_6 Product data sheet Pin function select register 0 (PINSEL0 - 0xE002 C000) Pin name Value P0. P0. P0. P0. P0. Rev. 06 — 11 December 2008 LPC2210/2220 16/32-bit ARM microcontrollers … ...
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... NXP Semiconductors Table 7. PINSEL0 31:30 6.7 Pin function select register 1 (PINSEL1 - 0xE002 C004) The PINSEL1 register controls the functions of the pins as per the settings listed in Table 8. The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically. ...
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... NXP Semiconductors Table 8. PINSEL1 15:14 17:16 19:18 21:20 23:22 25:24 27:26 29:28 31:30 LPC2210_2220_6 Product data sheet Pin function select register 1 (PINSEL1 - 0xE002 C004) Pin name Value P0. P0. P0. P0. P0. P0. P0. P0. P0. Rev. 06 — 11 December 2008 LPC2210/2220 16/32-bit ARM microcontrollers …continued Function Value after reset GPIO Port 0 ...
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... NXP Semiconductors 6.8 Pin function select register 2 (PINSEL2 - 0xE002 C014) The PINSEL2 register controls the functions of the pins as per the settings listed in Table 9. The direction control bit in the IODIR register is effective only when the GPIO function is selected for a pin. For other functions direction is controlled automatically. ...
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... NXP Semiconductors Table 9. Pin function select register 2 (PINSEL2 - 0xE002 C014) PINSEL2 bits Description 23 Controls whether P3.0/ port pin ( address line (1). 24 Controls whether P3.1/ port pin ( address line (1). 27:25 Controls the number of pins among P3.23/A23/XCLK and P3[22:2]/A2[22:2] that are address lines: ...
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... NXP Semiconductors • Optional conversion on transition on input pin or Timer Match signal. 6.11.2 ADC features available in LPC2210/01 and LPC2220 only • Every analog input has a dedicated result register to reduce interrupt overhead. • Every analog input can generate an interrupt once the conversion is completed. ...
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... NXP Semiconductors • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • ...
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... NXP Semiconductors While the SSP and SPI1 peripherals share the same physical pins not possible to have both of these two peripherals active at the same time. Application can switch on the fly from SPI1 to SSP and back. 6.16 General purpose timers The timer/counter is designed to count cycles of the peripheral clock (PCLK externally supplied clock and optionally generate interrupts or perform other actions at specifi ...
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... NXP Semiconductors 6.17 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time. ...
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... NXP Semiconductors controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an MR0 match occurs. ...
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... NXP Semiconductors 6.20.2 PLL The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input frequency is multiplied up into the range of 10 MHz to 60 MHz (LPC2210) and 10 MHz to 75 MHz (LPC2210/01 and LPC2220) with a Current Controlled Oscillator (CCO). The ...
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... NXP Semiconductors 6.20.5 Memory mapping control The memory mapping control alters the mapping of the interrupt vectors that appear beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the BANK0 external memory the on-chip static RAM. This allows code running in different memory spaces to have control of the interrupts. ...
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... NXP Semiconductors 6.21.1 EmbeddedICE Standard ARM EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol converter. EmbeddedICE protocol converter converts the remote debug protocol commands to the JTAG data needed to access the ARM core. ...
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... NXP Semiconductors 7. Limiting values Table 10. Limiting values reset In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply voltage (3.3 V) DDA(3V3) V analog input voltage IA V input voltage I I supply current ...
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... NXP Semiconductors 8. Static characteristics Table 11. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter V supply voltage (1.8 V) DD(1V8) V supply voltage (3.3 V) DD(3V3) V analog supply voltage DDA(3V3) (3.3 V) Standard port pins, RESET, RTCK I LOW-level input current IL I HIGH-level input current ...
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... NXP Semiconductors Table 11. Static characteristics +85 C for commercial applications, unless otherwise specified. amb Symbol Parameter I Power-down mode supply DD(pd) current 2 I C-bus pins V HIGH-level input voltage IH V LOW-level input voltage IL V hysteresis voltage hys V LOW-level output voltage OL I input leakage current ...
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... NXP Semiconductors Table 12. ADC static characteristics +85 C unless otherwise specified. ADC frequency 4.5 MHz. DDA(3V3) amb Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G E absolute error ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. Fig 5. ADC characteristics LPC2210_2220_6 Product data sheet ...
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... NXP Semiconductors 9. Dynamic characteristics Table 13. Dynamic characteristics +70 C for commercial applications +85 C for industrial applications, V amb [1] specified ranges. Symbol Parameter External clock f oscillator frequency osc T clock cycle time cy(clk) t clock HIGH time CHCX t clock LOW time CLCX t clock rise time ...
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... NXP Semiconductors Table 14. External memory interface dynamic characteristics pF amb Symbol Parameter Common to read and write cycles t XCLK HIGH to address valid CHAV time t XCLK HIGH to CS LOW time CHCSL t XCLK HIGH to CS HIGH CHCSH time t XCLK HIGH to address CHANV invalid time Read cycle parameters ...
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... NXP Semiconductors Table 14. External memory interface dynamic characteristics pF amb Symbol Parameter t BLS HIGH to data invalid BLSHDNV time t XCLK HIGH to data valid CHDV time t XCLK HIGH to WE LOW time CHWEL t XCLK HIGH to BLS LOW CHBLSL time t XCLK HIGH to WE HIGH CHWEH time ...
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... NXP Semiconductors 9.1 Timing XCLK CS addr data t CSLOEL OE Fig 6. External memory read access XCLK CS BLS/WE addr data OE Fig 7. External memory write access LPC2210_2220_6 Product data sheet t CSLAV OELAV t CHOEL t CSLDV t AVCSL t WELWEH t CSLWEL t BLSLBLSH t t CSLBLSL WELDV t CSLDV Rev. 06 — 11 December 2008 ...
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... NXP Semiconductors Fig 8. External clock timing (with an amplitude of at least V 9.2 LPC2210 power consumption measurements 60 I current DD (mA Test conditions: code executed from on-chip RAM; all peripherals are enabled in PCONP register; PCLK = CCLK/4. (1) 1.8 V core (typical) (2) 1.65 V core (typical) Fig 9. LPC2210 I ...
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... NXP Semiconductors 15 I current DD (mA Test conditions: Idle mode entered executing code from on-chip RAM; all peripherals are enabled in PCONP register; PCLK = CCLK/4. (1) 1.8 V core (typical) (2) 1.65 V core (typical) Fig 10. LPC2210 I in Idle mode measured at different frequencies (CCLK) and temperatures DD 500 ...
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... NXP Semiconductors 9.3 LPC2220 and LPC2210/01 power consumption measurements (mA Test conditions: code executed from on-chip RAM; all peripherals are enabled in PCONP register; PCLK = CCLK/4. (1) 1.8 V core (typical) (2) 1.8 V core (typical) (3) 1.65 V core (typical) Fig 12. LPC2220 and LPC2210/ (mA Test conditions: Idle mode entered executing code from on-chip RAM; all peripherals are enabled in PCONP register; ...
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... NXP Semiconductors 200 I DD(pd 150 100 Test conditions: Power-down mode entered executing code from on-chip RAM; all peripherals are enabled in PCONP register. Fig 14. LPC2220 and LPC2210/01 I LPC2210_2220_6 Product data sheet Power-down mode measured at different temperatures DD Rev. 06 — 11 December 2008 LPC2210/2220 16/32-bit ARM microcontrollers 002aad389 1 ...
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... NXP Semiconductors 10. Package outline LQFP144: plastic low profile quad flat package; 144 leads; body 1 108 109 pin 1 index 144 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors TFBGA144: plastic thin fine-pitch ball grid array package; 144 balls ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) UNIT max 1.20 0.40 0.80 mm nom 1.05 0.35 0.70 min 0.95 0.30 0.65 OUTLINE VERSION IEC SOT569-2 Fig 16. Package outline SOT569-2 (TFBGA144) ...
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... NXP Semiconductors 11. Abbreviations Table 16. Acronym ADC AMBA APB CISC FIFO GPIO I/O JTAG PWM RISC SPI SSI SRAM TTL UART LPC2210_2220_6 Product data sheet Acronym list Description Analog-to-Digital Converter Advanced Microcontroller Bus Architecture Advanced Peripheral Bus Complex Instruction Set Computer First In, First Out ...
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... NXP Semiconductors 12. Revision history Table 17. Revision history Document ID Release date LPC2210_2220_6 20081211 • Modifications: Figure 8 “External clock timing (with an amplitude of at least V figure note row “V • Table 11 “Static • Table 11 “Static • Maximum frequency f • Changed SOT569-1 to SOT569-2. • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 15. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Key features . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 Functional description . . . . . . . . . . . . . . . . . . 15 6.1 Architectural overview 6.2 On-chip SRAM . . . . . . . . . . . . . . . . . . . . . . . . 15 6.3 Memory map 6.4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 16 6 ...