LPC2220FBD144 NXP Semiconductors, LPC2220FBD144 Datasheet - Page 25

• Manufacturer Part Number: LPC2220FBD144
• Description: IC, 16/32BIT ARM7 MCU, 64K RAM, SMD
• Manufacturer: NXP Semiconductors

Specifications of LPC2220FBD144

• No. Of I/o's: 76
• Ram Memory Size: 64KB
• Cpu Speed: 75MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 6
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Core Size: 32bit
• Oscillator Type: External Only
• Controller Family/series: LPC22xx
• Peripherals: ADC, RTC
• Rohs Compliant: Yes

NXP Semiconductors
LPC2210_2220_6
Product data sheet
6.14.1 Features
6.15.1 Features
6.15.2 Description
6.14 SPI serial I/O controller
6.15 SSP controller
The LPC2210/2220 each contain two SPIs. The SPI is a full duplex serial interface,
designed to be able to handle multiple masters and slaves connected to a given bus. Only
a single master and a single slave can communicate on the interface during a given data
transfer. During a data transfer the master always sends a byte of data to the slave, and
the slave always sends a byte of data to the master.
This peripheral is available in LPC2210/01 and LPC2220 only.
The SSP is a controller capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can
interact with multiple masters and slaves on the bus. Only a single master and a single
slave can communicate on the bus during a given data transfer. Data transfers are in
principle full duplex, with frames of 4 bits to 16 bits of data flowing from the master to the
slave and from the slave to the master.
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Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
Compliant with SPI specification.
Synchronous, serial, full duplex, communication.
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
Compatible with Motorola’s SPI, Texas Instrument’s 4-wire SSI, and National
Semiconductor’s Microwire buses.
Synchronous serial communication.
Master or slave operation.
8-frame FIFOs for both transmit and receive.
4 bits to 16 bits per frame.
2
C-bus may be used for test and diagnostic purposes.
Rev. 06 — 11 December 2008
16/32-bit ARM microcontrollers
LPC2210/2220
© NXP B.V. 2008. All rights reserved.
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