LPC2220FBD144 NXP Semiconductors, LPC2220FBD144 Datasheet - Page 11

• Manufacturer Part Number: LPC2220FBD144
• Description: IC, 16/32BIT ARM7 MCU, 64K RAM, SMD
• Manufacturer: NXP Semiconductors

Specifications of LPC2220FBD144

• No. Of I/o's: 76
• Ram Memory Size: 64KB
• Cpu Speed: 75MHz
• No. Of Timers: 2
• No. Of Pwm Channels: 6
• Digital Ic Case Style: LQFP
• Supply Voltage: RoHS Compliant
• Core Size: 32bit
• Oscillator Type: External Only
• Controller Family/series: LPC22xx
• Peripherals: ADC, RTC
• Rohs Compliant: Yes

NXP Semiconductors
Table 4.
LPC2210_2220_6
Product data sheet
Symbol
P1.26/RTCK
P1.27/TDO
P1.28/TDI
P1.29/TCK
P1.30/TMS
P1.31/TRST
P2.0 to P2.31
P2.0/D0
P2.1/D1
P2.2/D2
P2.3/D3
P2.4/D4
P2.5/D5
P2.6/D6
P2.7/D7
P2.8/D8
P2.9/D9
P2.10/D10
P2.11/D11
P2.12/D12
P2.13/D13
P2.14/D14
P2.15/D15
P2.16/D16
P2.17/D17
P2.18/D18
P2.19/D19
P2.20/D20
P2.21/D21
P2.22/D22
P2.23/D23
P2.24/D24
P2.25/D25
Pin description
Pin (LQFP)
52
144
140
126
113
43
98
105
106
108
109
114
115
116
117
118
120
124
125
127
129
130
131
132
133
134
136
137
1
10
11
12
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
…continued
Pin (TFBGA) Type
N6
B2
A3
A7
D10
M4
E12
C12
C11
B12
A13
C10
B10
A10
D9
C9
A9
A8
B7
C7
A6
B6
C6
D6
A5
B5
D5
A4
A1
E3
E2
E1
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
Rev. 06 — 11 December 2008
I/O
O
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Description
RTCK — Returned Test Clock output. Extra signal added to
the JTAG port. Assists debugger synchronization when
processor frequency varies. Bidirectional pin with internal
pull-up.
Note: LOW on this pin while RESET is LOW, enables pins
P1[31:26] to operate as Debug port after reset.
TDO — Test Data out for JTAG interface.
TDI — Test Data in for JTAG interface.
TCK — Test Clock for JTAG interface. This clock must be
slower than
to operate.
TMS — Test Mode Select for JTAG interface.
TRST — Test Reset for JTAG interface.
Port 2 — Port 2 is a 32-bit bidirectional I/O port with individual
direction controls for each bit. The operation of port 2 pins
depends upon the pin function selected via the Pin Connect
Block.
D0 — External memory data line 0.
D1 — External memory data line 1.
D2 — External memory data line 2.
D3 — External memory data line 3.
D4 — External memory data line 4.
D5 — External memory data line 5.
D6 — External memory data line 6.
D7 — External memory data line 7.
D8 — External memory data line 8.
D9 — External memory data line 9.
D10 — External memory data line 10.
D11 — External memory data line 11.
D12 — External memory data line 12.
D13 — External memory data line 13.
D14 — External memory data line 14.
D15 — External memory data line 15.
D16 — External memory data line 16.
D17 — External memory data line 17.
D18 — External memory data line 18.
D19 — External memory data line 19.
D20 — External memory data line 20.
D21 — External memory data line 21.
D22 — External memory data line 22.
D23 — External memory data line 23.
D24 — External memory data line 24.
D25 — External memory data line 25.
1
6
of the CPU clock (CCLK) for the JTAG interface
16/32-bit ARM microcontrollers
LPC2210/2220
© NXP B.V. 2008. All rights reserved.
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