PIC24FJ256GB106-I/MR Microchip Technology, PIC24FJ256GB106-I/MR Datasheet - Page 47

• Manufacturer Part Number: PIC24FJ256GB106-I/MR
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-64
• Manufacturer: Microchip Technology
• Series: PIC® 24Fr

Specifications of PIC24FJ256GB106-I/MR

• Controller Family/series: PIC24
• No. Of I/o's: 51
• Ram Memory Size: 16KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Core Size: 16 Bit
• Program Memory Size: 256KB
• Peripherals: ADC, Comparator, PWM, RTC, Timer
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, SPI, UART/USART, USB OTG
• Number Of I /o: 51
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VFQFN, Exposed Pad
• Processor Series: PIC24FJ
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240011
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

6.2
Checksums for the PIC24FJXXXGA1/GB1 families are
16 bits in size. The checksum is calculated by summing
the following:
• Contents of code memory locations
• Contents of Configuration registers
TABLE 6-4:
© 2007 Microchip Technology Inc.
PIC24FJ128GA106
PIC24FJ192GA106
PIC24FJ256GA106
PIC24FJ128GA108
PIC24FJ192GA108
PIC24FJ256GA108
PIC24FJ128GA110
PIC24FJ192GA110
PIC24FJ256GA110
PIC24FJ64GB106
PIC24FJ128GB106
PIC24FJ192GB106
PIC24FJ256GB106
PIC24FJ64GB108
Legend:
Note:
Checksum Computation
Device
Item
SUM[a:b]
CFGB
TBD
CW1 address is last location of implemented program memory; CW2 is (last location – 2); CW3 is (last
location – 4).
CHECKSUM COMPUTATION
=
=
=
Description
Byte sum of locations, a to b inclusive (all 3 bytes of code memory)
CFGB = Configuration Block (masked) Byte sum of (CW1 & 0x7BDF + CW2 & 0xF7FF +
CW3 & 0xE1FF)
To Be Determined
Read Code
Protection
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Checksum Computation
CFGB + SUM(0:20BF9)
CFGB + SUM(0:2ABF9)
CFGB + SUM(0:20BF9)
CFGB + SUM(0:2ABF9)
CFGB + SUM(0:20BF9)
CFGB + SUM(0:2ABF9)
CFGB + SUM(0:20BF9)
CFGB + SUM(0:2ABF9)
CFGB + SUM(0:1F7F9)
CFGB + SUM(0:1F7F9)
CFGB + SUM(0:1F7F9)
CFGB + SUM(0:1F7F9)
CFGB + SUM(0:ABF9)
CFGB + SUM(0:ABF9)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PIC24FJXXXGA1/GB1
Table 6-4 describes how to calculate the checksum for
each device. All memory locations are summed, one
byte at a time, using only their native data size. More
specifically, Configuration registers are summed by
adding the lower two bytes of these locations (the
upper byte is ignored), while code memory is summed
by adding all three bytes of code memory.
Checksum
Erased
Value
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0xAAAAAA at 0x0
Checksum with
and Last Code
DS39907A-page 47
Address
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD