SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet
SW00ENB-ZCC
Specifications of SW00ENB-ZCC
Related parts for SW00ENB-ZCC
SW00ENB-ZCC Summary of contents
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TX System RISC TX19 Family TMP1940CYAF/TMP1940FDBF ...
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... It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications ...
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... Application Specific Extension pioneered by MIPS Technologies, Inc. Recently, with the ever-growing market for lightweight portable devices, manufacturers of electronic systems have been seeking cost-effective, single-chip solutions to processor-based applications. Toshiba has designed the TX1940 to help customers achieve the best cost performance for their products. Preface ...
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Handling Precaution Part 1 TMP1940 TMP1940CYAF 1. Features ................................................................................................................................................................... 1 2. Signal Descriptions ................................................................................................................................................. 5 2.1 Pin Assignment .................................................................................................................................................. 5 2.2 Pin Usage Information ....................................................................................................................................... 6 3. Core Processor ........................................................................................................................................................ 9 3.1 Reset Operation ................................................................................................................................................. 9 4. Memory Map......................................................................................................................................................... 10 ...
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TMP1940 7.6 Port 5 (P50–P57) ............................................................................................................................................. 53 7.7 Port 7 (P70–P77) ............................................................................................................................................. 54 7.8 Port 8 (P80–P87) ............................................................................................................................................. 58 7.9 Port 9 (P90–P97) ............................................................................................................................................. 61 7.10 Port A (PA0–PA7) ........................................................................................................................................... 66 7.11 Open-Drain Output Control ............................................................................................................................. 71 8. External Bus ...
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Prescaler................................................................................................................................................ 118 11.2.2 Up-Counters (UC0 and UC1) ............................................................................................................... 119 11.2.3 Timer Registers (TA0REG and TA1REG) ............................................................................................ 119 11.2.4 Comparators (CP0 and CP1)................................................................................................................. 120 11.2.5 Timer Flip-Flop (TA1FF)...................................................................................................................... 120 11.3 Register Description ...................................................................................................................................... 121 11.4 Operating Modes ........................................................................................................................................... 126 11.4.1 ...
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TMP1940 14.5.1 Acknowledgment Mode ........................................................................................................................ 205 14.5.2 Number of Bits Per Transfer ................................................................................................................. 205 14.5.3 Serial Clock........................................................................................................................................... 205 14.5.4 Slave Addressing and Address Recognition Mode ............................................................................... 206 14.5.5 Configuring the SBI as a Master or a Slave .......................................................................................... 206 14.5.6 ...
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SBI Timing .................................................................................................................................................... 256 2 18.7.1 C Mode .............................................................................................................................................. 256 I 18.7.2 Clock-Synchronous 8-Bit SIO Mode .................................................................................................... 257 18.8 Event Counters (TA0IN, TA2IN, TB0IN0, TB0IN1, TB2IN0)..................................................................... 258 18.9 Timer Capture (TB0IN0, TB0IN1, TB1IN0, TB1IN1, TB2IN0, TB2IN1) .................................................. 258 18.10 ...
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TMP1940 TMP1940FDBF 1. Features ................................................................................................................................................................... 1 2. Signal Descriptions ................................................................................................................................................. 5 2.1 Pin Assignment .................................................................................................................................................. 5 2.2 Pin Usage Information ....................................................................................................................................... 6 3. Flash Memory ....................................................................................................................................................... 10 3.1 Features............................................................................................................................................................ 10 3.2 Block Diagram................................................................................................................................................. 11 3.3 Operating Modes ............................................................................................................................................. 12 3.3.1 ...
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Programmer Mode........................................................................................................................................... 69 3.7.1 Mode Setting........................................................................................................................................... 69 3.7.2 Memory Maps......................................................................................................................................... 70 3.7.3 Pin Functions and Settings ...................................................................................................................... 71 3.7.4 Key Features ........................................................................................................................................... 73 3.7.5 Block Architecture .................................................................................................................................. 74 3.7.6 Read Mode and Embedded Operation Mode .......................................................................................... 75 3.7.7 Reading ...
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TMP1940 viii ...
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Handling Precautions ...
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...
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... It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications ...
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Safety Precautions This section lists important precautions which users of semiconductor devices (and anyone else) should observe in order to avoid injury and damage to property, and to ensure safe and correct use of devices. Please be sure that ...
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General Precautions regarding Semiconductor Devices Do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature). This may cause the device to break down, degrade its performance, or cause it to catch ...
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Precautions Specific to Each Product Group 2.2.1 Optical semiconductor devices When a visible semiconductor laser is operating, do not look directly into the laser beam or look through the optical system. This is highly likely to impair vision, and ...
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Do not use devices under conditions which exceed their absolute maximum ratings (current, voltage, power dissipation, temperature etc.). This may cause the device to break down, causing a large short-circuit current to flow, which may in turn cause it to ...
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General Safety Precautions and Usage Considerations This section is designed to help you gain a better understanding of semiconductor devices ensure the safety, quality and reliability of the devices which you incorporate into your designs. 3.1 ...
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Make sure that sections of the tape carrier which come into contact with installation devices or other electrical machinery are made of a low-resistance material. (f) Make sure that jigs and tools used in the assembly process do not ...
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When storing printed circuit boards which have devices mounted on them, use a board container or bag that is protected against static charge. To avoid the occurrence of static charge or discharge due to friction, keep the boards separate from ...
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Storage 3.2.1 General storage Avoid storage locations where devices will be exposed to moisture or direct sunlight. Follow the instructions printed on the device cartons regarding transportation and storage. The storage area temperature should be kept within a temperature ...
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If the 12-month storage period has expired the 30% humidity indicator shown in Figure 1 is pink when the packing is opened, it may be advisable, depending on the device and packing type, to back the devices at ...
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... This section describes some general precautions which you should observe when designing circuits and when mounting devices on printed circuit boards. For more detailed information about each product family, refer to the relevant individual technical datasheets available from Toshiba. 3.3.1 Absolute maximum ratings Do not use devices under conditions in which their absolute maximum ratings (e ...
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CMOS logic IC inputs, for example, have extremely high impedance input pin is left open, it can easily pick up extraneous noise and become ...
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... For details of how to interface particular devices, consult the relevant technical datasheets and databooks. If you have any questions or doubts about interfacing, contact your nearest Toshiba office or distributor. 3 General Safety Precautions and Usage Considerations ...
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Decoupling Spike currents generated during switching can cause Vcc (Vdd) and GND (Vss) voltage levels to fluctuate, causing ringing in the output waveform or a delay in response speed. (The power supply and GND wiring impedance is normally 50 ...
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These include installing shields and noise filters, and increasing the thickness of the power supply wiring patterns on the printed circuit board. One effective ...
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Inspection Sequence ! Do not insert devices in the wrong orientation. Make sure that the positive and negative electrodes of the power supply are correctly connected. Otherwise, the rated maximum current or maximum power dissipation may be exceeded and ...
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Lead insertion hole intervals on the printed circuit board should match the lead pitch of the device precisely. (2) If lead insertion hole intervals on the printed circuit board do not precisely match the lead pitch of the device, ...
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Using a soldering iron Complete soldering within ten seconds for lead temperatures 260°C, or within three seconds for lead temperatures 350°C. (2) Using medium infrared ray reflow Heating top and bottom with long ...
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Figure 5 shows an example of a recommended temperature profile for surface-mount packages using solder flow. Figure 5 Sample temperature profile for solder flow 3.5.4 Flux cleaning and ultrasonic cleaning ...
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... When handling chips, be careful not to expose them to static electricity. In particular, measures must be taken to prevent static damage during the mounting of chips. With this in mind, Toshiba recommend mounting all peripheral parts first and then mounting chips last (after all other components have been mounted). ...
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... Two recommended silicone compounds in which base oil separation is not a problem are YG6260 from Toshiba Silicone. (6) Heat-sink-equipped devices can become very hot during operation. Do not touch them, or you may sustain a burn. ...
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Protecting Devices in the Field 3.6.1 Temperature Semiconductor devices are generally more sensitive to temperature than are other electronic components. The various electrical characteristics of a semiconductor device are dependent on the ambient temperature at which the device is ...
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Interference from light (ultraviolet rays, sunlight, fluorescent lamps and incandescent lamps) Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases the device can malfunction. This is especially true for devices in which the ...
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... Using resonators which are not specifically recommended for use Resonators recommended for use with Toshiba products in microcontroller oscillator applications are listed in Toshiba databooks along with information about oscillation conditions. If you use a resonator not included in this list, please consult Toshiba or the resonator manufacturer concerning the suitability of the device for your application ...
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... C/W) Note 1: If you use a microcontroller device outside the range for long periods of time, contact your nearest Toshiba office or authorized Toshiba dealer. Note 2: For the •ja value, contact your nearest Toshiba office or authorized Toshiba dealer. 25 ...
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Precautions and Usage Considerations Specific to Each Product Group 26 ...
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Part 1 TMP1940 ...
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...
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... TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications ...
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RAM 256-Kbyte on-chip ROM (The TMP1940FDBF has 512-Kbyte FE (3) External memory expansion 16-Mbyte off-chip address space for code and data External bus interface with dynamic bus sizing for 8-bit and 16-bit data ports (4) 4-channel DMA ...
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Operating voltage range: 2.7 to 3.6 V (20) Operating frequency 32 MHz (Vcc 3 MHz (Vcc 2.7 V) (21) Package 100-pin QFP ( 1.4 (t) mm, 0.5-mm pitch) TMP1940CYAF-3 TMP1940CYAF ...
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ROM DMAC (4ch) NMI INT0 (P77) INTC INT1-4 (PA0-3) INT5-A, (P74-5, P80-1, P83-4) EBIF ADTRG (P53) (P50 P57) 10-Bit AN0 AN7 ADC AVCC, AVSS VREFH, VREFL TXD0 (P90) RXD0 (P91) SIO0 (P92) SCLK0/ CTS0 TXD1 (P93) RXD1 (P94) SIO1 ...
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Signal Descriptions This section contains pin assignments for the TMP1940CYAF as well as brief descriptions of the TMP1940CYAF input and output signals. 2.1 Pin Assignment The following illustrates the TMP1940CYAF pin assignment. DVSS 89 P50/AN0 90 P51/AN1 91 P52/AN2 ...
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Pin Usage Information Table 2.1 lists the input and output pins of the TMP1940CYAF, including alternate pin names and functions for multi-function pins. Pin Name # of Pins Type P00–P07 8 Input/output AD0–AD7 Input/output P10–P17 8 Input/output AD8–AD15 Input/output ...
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Pin Name # of Pins Type P72 1 Input/output TA2IN Input TXD4 Output P73 1 Input/output TA3OUT Output RXD4 Input P74 1 Input/output TB0IN0 Input INT5 Input P75 1 Input/output TB0IN1 Input INT6 Input P76 1 Input/output TB0OUT Output P77 ...
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Pin Name # of Pins Type P92 1 Input/output SCLK0 Input/output CTS 0 Input P93 1 Input/output TXD1 Output P94 1 Input/output RXD1 Input P95 1 Input/output SCLK1 Input/output CTS 1 Input P96 1 Input/output XT1 Input P97 1 Input/output ...
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Core Processor The TMP1940CYAF contains a high-performance 32-bit core processor called the TX19. For a detailed description of the core processor, refer to the 32-Bit TX System RISC TX19 Core Architecture manual. Functions unique to the TMP1940CYAF, which are ...
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Memory Map The mapping of virtual addresses to physical addresses is shown below. Virtual Address 0xFFFF_FFFF 16 Mbytes Reserved 0xFF00_0000 Kseg2 0xBFC4_0000 0xBFC0_0000 Kseg1 0xA000_0000 Kseg0 0x8000_0000 16 Mbytes Reserved Kuseg 0x0003_FFFF 0x0000_0000 Note 1: In the TMP1940CYAF, the ...
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Clock/Standby Control The TMP1940CYAF has two clocking modes: Single-Clock mode which operates off of the high-speed clock supplied from the X1/X2 pins, and Dual-Clock mode which operates off of the high-speed clock supplied from the X1/X2 pins and the ...
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Clock Generation 5.1.1 Main System Clock A crystal can be connected between X1 and X2 can be externally driven with a clock. The on-chip PLL can be enabled or disabled (bypassed) during reset by using the PLLOFF ...
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Clock Source Block Diagrams SYSCR0.WUEF SYSCR2.WUPT[1:0] SYSCR3.LUPTM Warm-up Timer SYSCR0. Lock (PLL) Timer XTEN fs Low- XT1 Speed XT2 fpll Oscillator SYSCR0. PLL XEN High- X1 Speed 2 X2 Oscillator fosc SYSCR1.DFOSC fsys fperiph Note 1: ...
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Clock Generator (CG) Registers 5.2.1 System Clock Control Registers 7 SYSCR0 Name XEN (0xFFFF_EE00) Read/Write Reset Value 1 Function High-speed oscillator 0: Disable 1: Enable 15 SYSCR1 Name (0xFFFF_EE01) Read/Write Reset Value Function 23 SYSCR2 Name DRVSOCH DRVOSCL (0xFFFF_EE02) ...
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Note 1: The Config register in the CP0 has the Doze and Halt bits. Setting the Halt bit puts the TMP1940CYAF in one of the standby modes, as specified by the STBY1-STBY0 bits in the SYSCR2. Setting the Doze bit ...
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ADC Conversion Clock 7 ADCCLK Name (0xFFFF_EE04) Read/Write Reset Value Function Note: A/D conversion is executed using the clock selected by this register. Reduced conversion accuracy occurs unless the conversion time is set to 8.6 µs or more. Relationships ...
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IMCGA3 Name (0xFFFF_EE13) Read/Write Reset Value Function 7 IMCGB0 Name (0xFFFF_EE14) Read/Write Reset Value Function 15 IMCGB1 Name (0xFFFF_EE15) Read/Write Reset Value Function 23 IMCGB2 Name (0xFFFF_EE16) Read/Write Reset Value Function 31 IMCGB3 Name (0xFFFF_EE17) Read/Write Reset Value Function ...
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Example: Enabling the INT0 interrupt IMCGA0.EMCG[01:00 IMCGA0.INT0EN = 1 IMC0L.EIM[11:10 IMC0L.IL[12:10] = 101 All interrupt sources other than those used for STOP/SLEEP wake-up signaling are controlled by the INTC block. 5.2.4 Interrupt Request Clear Register 7 ...
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System Clock Control Section A system reset initializes the SYSCR0.XEN bit to 1, the SYSCR0.XTEN bit to 0 and the SYSCR1.GEAR[1:0] bits to 00, putting the TMP1940CYAF in Single-Clock mode. If the on-chip PLL is enabled, the PLL reference ...
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Example: Switching from NORMAL mode to SLOW mode SYSCR2.WUPT[1: SYSCR0.XTEN = 1 SYSCR0.WUEF = 1 Check SYSCR0.WUEF. SYSCR1.SYSCK = 1 SYSCR0.XEN = 0 5.3.2 System Clock Output Either the fsys or fs clock can be driven out from ...
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Drive capability of the high-speed oscillator C1 Crystal C2 Drive capability of the low-speed oscillator C1 Crystal C2 Figure 5.4 Oscillator Clock Drive Capabilities 5.4 Prescalar Clock Control Section The TMRA01, TMRA23, TMRB0 to TMRB3, SIO0 to SIO4 (there is ...
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There is one thing to remember when changing the clock gear value. The clock gear can be changed by the programming of the GEAR[1:0] bits of the SYSCR1. The RF[1:0] bits of the CPU’s Config register need not be altered. ...
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TMP1940CYAF Operation in NORMAL and Standby Modes Table 5.4 TMP1940CYAF Operation in NORMAL and Standby Modes Operation Mode NORMAL The TX19 core processor and peripherals operate at frequencies specified in the CG block. IDLE (Halt) The processor and DMAC ...
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Wake-up Signaling There are two ways to exit a standby mode: an interrupt request or reset signal. Availability of wake- up signaling depends on the settings of the Interrupt Mask Level bits, CMask[15:13], of the CP0 Status register and ...
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Table 5.7 Wake-up Signaling Sources and Wake-up Operations Interrupt Masking Standby Mode (Programmable) NMI INTWDT INT0–4 INTRTC INT5–A INTTA0–3 INTTB00–31 INTTBOF0–3 INTRX0–4 INTTX0–4 INTS2 INTAD 2 INTDMA RESET : Execution resumes with the interrupt service routine Execution resumes ...
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STOP Mode The STOP mode stops the whole TMP1940CYAF, including the on-chip oscillator. Pin states in STOP mode depend on the setting of the SYSCR2.DRVE bit, as shown in Table 5.8. Upon detection of wake-up signaling, the warm-up period ...
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Mode transitions from SLOW to STOP to SLOW fsys (Low-speed clock) Mode SLOW CG (Low-speed clock) Warm-up (W-up) When fosc = 32.768 kHz W-up Time Select SYSCR2.WUPT[1: /fosc /fosc /fosc) ...
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Table 5.8 Pin States in STOP Mode Pins Input/Output P00–07 Input mode Output mode AD0–AD7 P10–17 Input mode Output mode AD8–AD15 P20–27 Input mode Output mode, A0–A7/A16–A23 P30 ( RD ), P31 ( WR ) Output pin P32–37 Input mode ...
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Interrupts 6.1 Overview Interrupt processing is coordinated bewtween the CP0 Status register, the Interrupt Controller (INTC) and the Clock Generator (CG). The Status register contains the Interrupt Mask Level field (CMask[15:13]) and the Interrupt Enable bit (IEc). For interrupt ...
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The INTxEN bit in the IMCGxx register controls whether these interrupt sources are enabled as wake-up signal sources (1=enable). If enabled, the interrupt polarity (EIMxx) field in the INTC’s IMCxx register has no effect, but must ...
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Interrupt Sources The TMP1940CYAF provides a reset interrupt, nonmaskable interrupts, and maskable interrupts: Reset and nonmaskable interrupts The RESET pin causes a Reset interrupt. The NMI pin functions as a nonmaskable interrupt. The on-chip Watchdog Timer (WDT) is also ...
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Table 6.1 Hardware Interrupt Sources Interrupt IVR[9:0] Number 0 000 Software Set 1 010 INT0 pin 2 020 INT1 pin 3 030 INT2 pin 4 040 INT3 pin 5 050 INT4 pin 6 060 Reserved 7 070 Reserved 8 080 ...
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Interrupt IVR[9:0] Number 54 360 INTRX3: SIO receive (Channel 3) 55 370 INTTX3: SIO transmit (Channel 3) 56 380 INTRX4: SIO receive (Channel 4) 57 390 INTTX4: SIO transmit (Channel 4) 58 3A0 INTRTC: RTC 59 3B0 INTAD: A/D conversion ...
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Register Description Address Symbol 0xFFFF_E060 INTCLR 0xFFFF_E040 IVR 0xFFFF_E03C IMCF 0xFFFF_E038 IMCE 0xFFFF_E034 IMCD 0xFFFF_E030 IMCC 0xFFFF_E02C IMCB 0xFFFF_E028 IMCA 0xFFFF_E024 IMC9 0xFFFF_E020 IMC8 0xFFFF_E01C IMC7 0xFFFF_E018 IMC6 0xFFFF_E014 IMC5 0xFFFF_E010 IMC4 0xFFFF_E00C IMC3 0xFFFF_E008 IMC2 0xFFFF_E004 IMC1 0xFFFF_E000 ...
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Interrupt Mode Control Registers (IMCF–IMC0) These registers control the interrupt priority level, active polarity, either level or edge sensitivity, and DMA triggering. 7 IMC0L Name (0xFFFF_E000) Read/Write Reset Value Function 15 Name Read/Write Reset Value Function 23 IMC0H Name ...
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I/O Ports The TMP1940CYAF has 77 I/O port pins. All the port pins except a few share pins with alternate functions. They can be individually programmed as general-purpose I/O or dedicated I/O for the on-chip CPU or peripherals. Table ...
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Table 7.2 I/O Port Programmability (1/2) Port Pin Name Direction / Function P00–P07 Input port Port 0 Output port AD0–AD7 bus lines P10–P17 Input port Output port Port 1 AD8–AD15 bus lines A8–A15 outputs P20–P27 Input port Output port Port ...
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Table 7.2 I/O Port Programmability (2/2) Port Pin Name P80–P87 Input port Output port TB1IN0 input P80 INT7 input P81 TB1IN1 input INT8 input Port 8 P82 TB1OUT output P83 TB2IN0 input INT9 input P84 TB2IN1 input INTA input P85 ...
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Note 1: P32, P36 and P40–P43 have their internal pull-up resistors enabled when the corresponding PxFC register bit is set and when the bus is released. Note 2: When P50–P57 are configured as analog channels of the ADC, the ADCH[2:0] ...
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Port 0 (P00–P07) Eight Port 0 pins function as either discrete general-purpose I/O pins or the AD[0:7] bits of the address/data bus. The P0CR register controls the direction of the Port 0 pins. Upon reset, the P0CR register bits ...
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P0 Name P07 (0xFFFF_F000) Read/Write Reset Value 7 P0CR Name P07 (0xFFFF_F002) Read/Write Reset Value 0 Function 0: IN, 1: OUT (Functions as AD7–AD0 during external memory accesses, with all bits cleared.) Port 0 Register ...
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Port 1 (P10–P17) Eight Port 1 pins can be individually programmed to function as discrete general-purpose I/O pins, the AD[8:15] bits of the address/data bus or the A[8:15] bits of the address bus. The P1CR and P1FC registers select ...
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P1 Name P17 (0xFFFF_F001) Read/Write Reset Value 7 P1CR Name P17C (0xFFFF_F004) Read/Write Reset Value 0 Function 7 P1FC Name P17F (0xFFFF_F005) Read/Write Reset Value 0 Function Port 1 Register P16 P15 P14 P13 R/W ...
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Port 2 (P20–P27) Eight Port 2 pins can be individually programmed to function as discrete general-purpose I/O pins, the A[0:7] bits of the address bus or the A[16:23] bits of the address bus. The P2CR and P2FC registers select ...
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P2 Name P27 (0xFFFF_F012) Read/Write Reset Value 7 P2CR Name P27C (0xFFFF_F014) Read/Write Reset Value 0 Function 7 P2FC Name P27F (0xFFFF_F015) Read/Write Reset Value 0 Function Port 2 Register P26 P25 P24 P23 R/W ...
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Port 3 (P30–P37) Eight Port 3 pins can be individually programmed to function as either discrete general-purpose I/O pins or CPU control/status pins. In either case, P30 and P31 are output-only pins. The P3CR and P3FC registers select the ...
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Reset Function Control (bitwise) P3CR Write Output Latch B P3 Write Read Reset Direction Control (bitwise) P3CR Write Function Control (bitwise) P3FC Write Output Latch B P3 Write HWR , ...
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Reset Direction Control (bitwise) P3CR Write S Output Latch Output Buffer P3 Write P3 Read Internal WAIT Reset Direction Control (bitwise) P3CR Write Function Control (bitwise) P3FC Write S Output Latch P3 Write P3 Read Internal BUSRQ Figure 7.8 Port ...
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P3 Name P37 (0xFFFF_F018) Read/Write Reset Value 1 (Pullup) 7 Name P37C P3FC (0xFFFF_F01B) Read/Write Reset Value 0 Function 7 Name P3FC (0xFFFF_F01B) Read/Write Reset Value Function Port 3 Register P36 P35 P34 R/W Input mode ...
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Port 4 (P40–P44) P40–P43 can be individually programmed to function as either discrete general-purpose I/O pins or programmable chip select ( CS0 – CS3 ) pins. P44 can be programmed to function as either a general-purpose I/O pin or ...
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Reset Direction Control (bitwise) P4CR Write Function Control (bitwise) P4FC Write S Output Latch P4 Write S B Selector Read A fsys Clock Y Selector fs Clock B S SYSCR3.SCOSEL Figure 7.11 Port 4 (P44) TMP1940CYAF-51 TMP1940CYAF ...
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P4 Name (0xFFFF_F01E) Read/Write Reset Value 7 P4CR Name (0xFFFF_F020) Read/Write Reset Value 7 P4FC Name (0xFFFF_F021) Read/Write Reset Value Function Port 4 Register P44 P43 1 1 (Pullup) Port 4 Control Register 6 5 ...
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Port 5 (P50–P57) Eight Port 5 pins are input-only pins shared with the analog input pins of the A/D Converter (ADC). P53 is also shared with the A/D trigger input pin. Port 5 Read AD Read ADTRG (Only P53) ...
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Port 7 (P70–P77) Eight Port 7 pins can be individually programmed to function as discrete general-purpose or dedicated I/O pins. Upon reset, all Port 7 pins are configured as input port pins. Alternatively, P70 and P72 can each be ...
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Reset Direction Control (bitwise) P7CR Write Function Control (bitwise) P7FC Write S Output Latch P7 Write Timer Flip-Flop Output TA1OUT: From TMRA01 TA3OUT: From TMRA23 P7 Read RXD3 RXD4 Reset Direction Control (bitwise) P7CR Write Function Control (bitwise) P7FC Write ...
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Reset Direction Control (bitwise) P7CR Write Function Control (bitwise) P7FC Write S Output Latch P7 Write Timer Flip-Flop Output TB0OUT: From TMRB0 P7 Read Reset Direction Control (bitwise) P7CR Write Function Control (bitwise) P7FC Write S Output Latch P7 Write ...
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P7 Name P77 (0xFFFF_F02B) Read/Write Reset Value 1 7 P7CR Name P77C (0xFFFF_F02E) Read/Write Reset Value 0 Function 7 P7FC Name P77F (0xFFFF_F02F) Read/Write Reset Value 0 Function 0: Port 1: Wake-up INT0 INT0 Settings P7FC.P77F 1 P7CR.P77C 0 ...
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Port 8 (P80–P87) Eight Port 8 pins can be individually programmed to function as discrete general-purpose or dedicated I/O pins. Upon reset, all Port 8 pins are configured as input port pins, and the Output Latch (P8) is set ...
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Reset Direction Control (bitwise) P8CR Write Function Control (bitwise) P8FC Write S Output Latch P8 Write P8 Read TB1IN0 TB1IN1 TB2IN0 TB2IN1 INT7 INT8 INT9 INTA Reset Direction Control (bitwise) P8CR Write Function Control (bitwise) P8FC Write S Output Latch ...
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P8 Name P87 (0xFFFF_F030) Read/Write Reset Value 7 P8CR Name P87C (0xFFFF_F032) Read/Write Reset Value 0 Function 7 P8FC Name (0xFFFF_F033) Read/Write Reset Value Function Must be written as 0. TB3OUT Settings P8FC.P86F P8CR.P86C Port 8 Register 6 5 ...
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Port 9 (P90–P97) P90–P95 P90–P95 can be individually programmed to function as discrete general-purpose or dedicated I/O pins. Upon reset, P90–P95 are configured as input port pins, and the corresponding Output Latch (P9) bits are set to 1. Setting ...
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P91 (RXD0) and P94 (RXD1) P91 and P94 can be programmed to function as either general-purpose I/O pins or RXD input pins for SIO channels. Reset Direction Control (bitwise) P9CR Write S Output Latch P9 Write P9 Read RXD0, ...
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P92 (SCLK0/ CTS0 ) and P95 (SCLK1/ CTS1 ) P92 and P95 can be programmed to function as general-purpose I/O pins, or SCLK clock input or output pins or CTS input pins for SIO channels. Reset Direction Control (bitwise) ...
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P96 (XT1) and P97 (XT2) P96 and P97 function as general-purpose I/O pins. Alternatively, P96 and P97 can be used as the XT1 and XT2 pins for connecting a low-frequency crystal. Reset Direction Control P9CR Write Output Latch P9 ...
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P9 Name P97 (0xFFFF_F031) Read/Write Reset Value Output mode 1 7 P9CR Name P97C (0xFFFF_F034) Read/Write Reset Value 1 Function 7 P9FC Name (0xFFFF_F035) Read/Write Reset Value Function CTS1 /SCLK1 Input Settings SCLK1 Output Settings P9FC.P95F 1 P9FC.P95F P9CR.P95C ...
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Port A (PA0–PA7) Eight Port A pins can be individually programmed to function as discrete general-purpose or dedicated I/O pins. Upon reset, all Port A pins are configured as input port pins. Alternatively, PA0–PA3 can be programmed as external ...
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Reset Direction Control (bitwise) PACR Write Function Control (bitwise) PAFC Write S Output Latch PA Write Selector PA Read (Note) INT1–INT4 Reset Direction Control (bitwise) PACR Write S Output Latch Write Selector A PA Read Figure 7.26 ...
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Reset Direction Control (bitwise) PACR Write Function Control (bitwise) PAFC Write S Output Latch A PA Write B SCK Output PA Read SCK Input Reset Direction Control (bitwise) PACR Write Function Control (bitwise) PAFC Write S Output Latch A PA ...
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Reset Direction Control (bitwise) PACR Write Function Control (bitwise) PAFC Write S Output Latch PA Write SCL Output PA Read SI Input SCL Input S A Selector Configurable open-drain output ODE.ODEA7 S B Selector A Figure 7.28 ...
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PA Name PA7 (0xFFFF_F036) Read/Write Reset Value 7 PACR Name PA7C (0xFFFF_F038) Read/Write Reset Value 0 Function 7 PAFC Name PA7F (0xFFFF_F039) Read/Write Reset Value 0 Function 0: Port 1: SCL output SCL Output Settings PAFC.PA7F PACR.PA7C Port A ...
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Open-Drain Output Control The TXD output pins (P70, P72, P90 and P93) of the SIO, and the SO/SDA (PA6) and SI/SCL (PA7) pins of the Serial Bus Interface (SBI) can be configured as either push-pull or open-drain outputs. 7 ...
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External Bus Interface The TMP1940CYAF contains external bus interface logic that handles the transfer of information between the internal busses and the memory or peripherals in the external address space. It consists of the External Bus Interface (EBIF) logic ...
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Address and Data Buses 8.1.1 Supported Configurations For external memory interface, Port 0 (AD0–AD7), Port 1 (AD8–AD15/A8–A15) and Port 2 (A16– A23/A0–A7) pins can be configured as the address and data buses. The TMP1940CYAF supports the following four bus ...
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External Bus Operation This section describes external bus operations. In the timing diagrams which follow, A23–A16 is the address bus, and AD15–AD0 is the address/data bus. This section only provides a functional description of the bus; refer to Section ...
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Wait Timing The CS/Wait Controller provides two ways to insert wait states in a bus cycle. Each address block can be programmed either: to insert required number of wait state cycles (up to seven cycles use the ...
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Upper Address A[23:16] AD[15:0] ADR DATA ALE WR 0 Wait State Figure 8.5 Write Cycle Timing (with Zero and One Wait State Cycle) tsys A[23:16] Upper Address AD[15:0] ADR DATA ALE WR WAIT 0 Wait State Figure 8.6 Write ...
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ALE Pulse Width The ALE pulse width is programmed to 0.5 or 1.5 clock cycles through the ALESEL bit of the SYSCR3 register within the CG. The default is 1.5 cycles. This setting applies to the whole external address ...
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Read Recovery Time Following an external bus read cycle, a certain recovery time may be required before initiating the next external bus cycle. To allow for a read recovery time, one or two dummy cycles can be inserted between ...
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Bus Arbitration The TMP1940CYAF provides support for an external bus master to take control of the external bus. Two bus arbitration control signals, BUSRQ and BUSAK , are used to determine the bus master. One or more of the ...
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Internal clock Internal address TMP1940CYAF external access External address TMP1940CYAF BUSRQ BUSAK Figure 8.11 Bus Arbitration Timing Diagram 1. BUSRQ is sampled high. 2. The TMP1940CYAF recognizes the assertion of BUSRQ . 3. The TMP1940CYAF asserts BUSAK at the ...
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Chip Select/Wait Controller The TMP1940CYAF supports direct connections to ROM and SRAM devices. The TMP1940CYAF provides four programmable chip select signals. Programmable features include variable block sizes, data bus width, wait state insertion, and dummy cycle insertion for back-to-back ...
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BMA0 Name (0xFFFF_E400) Read/Write Reset Value 1 Function 15 Name Read/Write Reset Value 0 Function 23 Name Read/Write Reset Value 0 Function 31 Name Read/Write Reset Value 0 Function 7 BMA1 Name (0xFFFF_E404) Read/Write Reset Value 1 Function 15 ...
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BMA2 Name (0xFFFF_E408) Read/Write Reset Value 1 Function 15 Name Read/Write Reset Value 0 Function 23 Name Read/Write Reset Value 0 Function 31 Name Read/Write Reset Value 0 Function 7 BMA3 Name (0xFFFF_E40C) Read/Write Reset Value 1 Function 15 ...
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Address 0xFFFF_FFFF 64 Kbytes 0x0000_0000 Figure 9.3 Relationships Between Starting Addresses and Base Address Register Values 9.1.2 Base Address and Address Mask Value Calculations Program the BMA0 register as follows to cause space starting at 0xC000_0000 ...
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Program the BMA2 register as follows to cause space starting at 0x1FC8_0000. 31 BA2 ...
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Table 9.1 shows the programmable block sizes for CS0 to CS3. Even if the user has accidentally programmed more than one chip select line to the same area, only one chip select line is driven because of internal line priorities. ...
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Chip Select/Wait Control Registers The organizations of the Chip Select/Wait Control registers are shown in Figure 9.4 to Figure 9.5. Each of these registers consist of a chip select type field, a master enable bit, a data bus width ...
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B23CS Name (0xFFFF_E484) Read/Write Reset Value 0 Function Chip select output waveform 00: ROM/RAM Don’t use any other value. 15 Name Read/Write Reset Value Function 23 Name B3OM Read/Write W Reset Value 0 Function Chip select output waveform 00: ...
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BEXCS Name BEXOM (0xFFFF_E488) Read/Write W Reset Value 0 Function Chip select output waveform 00: ROM/RAM Don’t use any other value. 15 Name Read/Write Reset Value Function Figure 9.6 Chip Select/Wait Control Registers 9.3 Application Example Figure 9.7 shows ...
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DMA Controller (DMAC) The TX1940CYAF contains a four-channel DMA controller. 10.1 Features The TMP1940CYAF DMAC has the following features: (1) Four independent DMA channels (2) Two types of bus requests, with and without bus snooping (3) Transfer requests: Internal ...
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Implementation 10.2.1 On-Chip DMAC Interface Figure 10.1 shows how the DMAC is internally connected with the TX19 core processor and the Interrupt Controller (INTC). TX19 Core Processor Bus Grant Bus Request Bus Release Request Bus Grant Ackowledge Control Address ...
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DMAC Block The DMAC block diagram is shown in Figure 10.2. Channel 3 Channel 2 Channel 1 31 Channel 0 Source ƒ A ƒ h ƒ Œ ƒ egi sut er 31 ƒ f ƒ X ƒ ...
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Register Description The DMAC has twenty-six 32-bit registers. The DMAC register map is shown in Table 10.1. Address 0xFFFF_E200 0xFFFF_E204 0xFFFF_E208 0xFFFF_E20C 0xFFFF_E210 0xFFFF_E218 0xFFFF_E220 0xFFFF_E224 0xFFFF_E228 0xFFFF_E22C 0xFFFF_E230 0xFFFF_E238 0xFFFF_E240 0xFFFF_E244 0xFFFF_E248 0xFFFF_E24C 0xFFFF_E250 0xFFFF_E258 0xFFFF_E260 0xFFFF_E264 0xFFFF_E268 ...
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DMA Control Register (DCR Rst W 15 Bits Mnemonic Field Name 31 Rst Reset Note 1: When the snoop request is disabled (CCRn.SReq=0), a software reset of the DMAC must be performed in the following sequence: 1. ...
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Channel Control Registers (CCRn Str ExR PosE Lev Sreq ReIEN R/W R/W R/W R/W R/W R Bits Mnemonic Field Name 31 Str Channel Start 24 ...
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Bit Mnemonic Field Name 11 SReq Snoop Request 10 RelEn Bus Release Request Enable 9 SIO I/O Source 8:7 SAC Source Address Count 6 DIO I/O Destination Destination 5:4 DAC Address Count 3:2 TrSiz Transfer Size 1:0 DPS Device Port ...
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Channel Status Registers (CSRn Act Bit Mnemonic Field Name 31 Act Channel Active 23 NC Normal Completion 22 AbC Abnormal Completion 21 Reserved 20 BES Source Bus Error 19 BED Destination Bus Error ...
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Source Address Registers (SARn Bit Mnemonic Field Name 31:0 SAddr Source Address Figure 10.6 Source Address Registers (SARn) SAddr R/W 0 SAddr R/W Description Reset value: Contains the physical address of the source device. The address changes ...
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Destination Address Registers (DARn Bit Mnemonic Field Name 31:0 DAddr Destination Address Figure 10.7 Destination Address Registers (DARn) DAddr R/W 0 DAddr R/W Description Reset value: Contains the physical address of the destination device. The address changes ...
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Byte Count Registers (BCRn Bit Mnemonic Field Name 23:0 BC Byte Count Figure 10.8 Byte Count Registers (BCRn R/W Description Reset value: Contains the number of bytes left to transfer on a DMA ...
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DMA Transfer Control Registers (DTCRn Bit Mnemonic Field Name 5:3 DACM Destination Address Count Mode 2:0 SACM Source Address Count Mode Figure 10.9 DMA Transfer Control Registers (DTCRn DACM Description Selects the manner ...
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Data Holding Register (DHR Bit Mnemonic Field Name 31:0 DOT Data on Transfer Figure 10.10 Data Holding Register (DHR) DOT R/W DOT R/W Description Reset value: Contains data read from the source address during a dual-address operation. ...
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Operation This section describes the operation of the DMAC. 10.4.1 Overview The DMAC is a high-speed 32-bit DMA controller used to quickly move large blocks of data between I/O peripherals and memory without intervention of the TX19 core processor. ...
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Transfer Request Generation Each DMA channel supports two types of request generation methods: internal and external. Internal requests are those generated within the DMAC. The DMA channel is started as soon as the Str bit in the CCRn register ...
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Summary of Transfer Modes The DMAC can perform data transfers as follows according to the combination of mode settings. Transfer Request Edge/Level Address Mode Internal External Low Level (7) Address Change Options Address pointers can increment, decrement or remain ...
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Transfer Request Generation A DMA request must be issued for the DMAC to initiate a data transfer. Each DMA channel in the DMAC supports two types of request generation method: internal and external. In either request generation mode, once ...
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DMA Address Modes The TMP1940CYAF supports only dual-address mode in which both the source and destination devices are explicitly addressed. In dual-address mode, two bus transfers occur: a read from a source device and a write to the destination ...
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The 32 bits of data are buffered in the DHR until the destination write cycle occurs. Source and destination addresses can be programmed to increment or decrement after each transfer. The SARn and ...
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Normal Termination A DMA channel terminates by normal completion in the following case. Normal completion always occurs at the boundary of transfers programmed into the CCRn.TrSize field. Data transfers have terminated, with the BCRn decremented to 0. Abnormal Termination The ...
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DMA Channel Priority The DMAC provides a fixed priority for the four channels, with channel 0 always having the highest priority and channel 3 the lowest. For example, when transfer requests occur on channels 0 and 1 simultaneously, the ...
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Data Packing and Unpacking In dual-address mode, the internal 32-bit DHR allows the data to be packed and unpacked by the DMAC if the programmed transfer size is not equal to the device port size. For example ...
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DMA Transfer Timing All DMAC operations are synchronous to the rising edges of the internal system clock. 10.5.1 Dual-Address Mode Memory-to-memory transfer Figure 10.14 shows a DMA cycle from one external 16-bit memory to another, with the transfer size ...
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I/O-to-memory transfer Figure 10.16 shows a DMA cycle from an 8-bit I/O peripheral to a 16-bit memory, with the transfer size programmed to 16 bits. tsys A[23:16 AD[15:0] Addr Read Figure 10.16 I/O-to-Memory Transfer ...
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Programming Example The following illustrates the programming required to transfer data from an SIO receive buffer (SCnBUF) to the on-chip RAM. The assumptions are as follows: DMAC Settings: DMA channel used: Channel 0 Source address: SC1BUF Destination address: 0xFFFF_9800 ...
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Timers (TMRAs) The TMP1940CYAF has a four-channel 8-bit timer (TMRA0–TMRA3), which is comprised of two modules named TMRA01 and TMRA23. The TMRA01 contains the TMRA0 and the TMRA1, and the TMRA23 contains the TMRA2 and TMRA3. Each timer ...
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Block Diagrams Figure 11.1 TMRA01 Block Diagram TMP1940CYAF-116 TMP1940CYAF ...
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Figure 11.2 TMRA23 Block Diagram TMP1940CYAF-117 TMP1940CYAF ...
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Timer Components 11.2.1 Prescaler The TMRA01 has a 9-bit prescalar that slows the rate of a clocking source to the counters. The prescalar clock source ( T0 can be selected from fperiph, fperiph/2 and fperiph/4 by programming the PRCK[1:0] ...
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Up-Counters (UC0 and UC1) The timer module contains two 8-bit binary up-counters, each of which is driven by a clock independently selected by the TA01MOD register. The clock input to the UC0 is either one of three prescalar outputs ...
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The addresses of the timer registers are as follows: TA0REG: 0xFFFF_F102 TA1REG: 0xFFFF_F103 TA2REG: 0xFFFF_F10A TA3REG: 0xFFFF_F10B The timer registers are write-only registers. 11.2.4 Comparators (CP0 and CP1) The comparator compares the output of the 8-bit up-counter with a time ...
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Register Description 7 TA01RUN Name TA0RDE (0xFFFF_F100) Read/Write R/W Reset Value 0 Double Buffering Function 0: Disable 1: Enable Note: Bits 4, 5 and 6 are read as undefined. 7 TA23RUN Name TA2RDE (0xFFFF_F108) Read/Write R/W Reset Value 0 ...
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TA01MOD TA01M1 Name (0xFFFF_F104) Read/Write 0 Reset Value Operating mode 00: 8-bit interval timer 01: 16-bit interval timer Function 10: 8-bit PPG 11: 8-bit PWM TMRA01 Mode Register TA01M0 PWM01 PWM00 TA1CLK1 R ...
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TA23MOD Name TA23M1 (0xFFFF_F10C) Read/Write Reset Valu 0 Operating mode 00: 8-bit interval timer Function 01: 16-bit interval timer 10: 8-bit PPG 11: 8-bit PWM TMRA23 Mode Register TA23M0 PWM21 PWM20 TA3CLK1 R ...
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TMRA01 Timer Flip-Flop Control Register 7 TA1FFCR Name (0xFFFF_F105) Read/Write Reset Value Function Note: Bits are read as undefined. Figure 11.7 TMRA01 Flip-Flop Control Register TAFF1C1 1 00: Toggles TA1FF. (software toggle) 01: ...
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TA3FFCR Name (0xFFFF_F10D) Read/Write Reset Value Function Note: Bits are read as undefined values. Figure 11.8 TMRA23 Flip-Flop Control Register TMRA23 Flip-Flop Control Register TAFF3C1 00: Toggles TA3FF (software toggle). 01: Sets TA3FF ...
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Operating Modes 11.4.1 8-Bit Interval Timer Mode The TMRA0 and the TMRA1 can be independently programmed as 8-bit interval timers. Programming these timers should only be attempted when the timers are not running. (1) Generating Periodic Interrupts In the ...
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Generating a SquareWave with a 50% Duty Cycle The 8-bit interval timer mode can be used to generate square-wave output. This is accomplished by toggling the timer flip-flop (TA1FF) periodically. The TA1FF state can be driven out to the ...
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Using the TMRA0 Match-Detect Output as a Trigger for the TMRA1 Set the TMRA01 in 8-bit interval timer mode. Select the TMRA0 comparator match-detect output (TA0TRG) as the clock source for the TMRA1. TMRA0 Comparator Match Output TMRA0 Up-Counter ...
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Programmable Pulse Generation (PPG) Mode The 8-bit PPG mode can be used to generate a square wave with any frequency and duty cycle, as shown below. The pulse can be high-going and low-going, as determined by the initial ...
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In 8-bit PPG mode, if the double-buffering function is enabled, the TA0REG value can be changed dynamically by writing a new value into the register buffer. Upon a match between the TA1REG and the UC0, the TA0REG latches a new ...
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PWM Generation Mode The TMRA0 can be used as a pulse-width modulated (PWM) signal generator with bits of resolution. This mode is supported by the TMRA0, but not by the TMRA1. The PWM signal is ...
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In 8-bit PWM generation mode, if the double-buffering function is enabled, the TA0REG value (i.e., the duty cycle) can be changed dynamically by writing a new value into the register buffer. Upon a 2 counter overflow, the TA0REG latches a ...
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Peripheral Prescaler Clock Gear Clock Clock Value Select Source SYSCR1. SYSCR1. SYSCR0. GEAR[1:0] FPSEL PRCK[1:0] 00 (fc) 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 01 (fc/2) 00 (fperiph/4) 01 (fperiph/2) 10 (fperiph) 0 (fgear) 10 (fc/4) 00 (fperiph/4) 01 (fperiph/2) 10 ...
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Operating Mode Summary Table 11.4 shows the settings for the TMRA01 for each of the operating modes. Table 11.4 Register Settings for Each Operating Mode Register Field TA01M[1:0] Interval Timer Function Mode 8-Bit Timer 2ch 00 16-Bit Timer Mode ...
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Timer/Event Counters (TMRBs) The TMP1940CYAF has a 16-bit timer/event counter consisting of four identical channels (TMRB0– TMRB3). Each channel has the following three basic operating modes: 16-bit interval timer mode 16-bit event counter mode 16-bit programmable pulse generation ...
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Block Diagrams Figure 12.1 TMRB0 Block Diagram TMP1940CYAF-136 TMP1940CYAF ...
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Figure 12.2 TMRB1 Block Diagram TMP1940CYAF-137 TMP1940CYAF ...
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Figure 12.3 TMRB2 Block Diagram TMP1940CYAF-138 TMP1940CYAF ...
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Figure 12.4 TMRB3 Block Diagram TMP1940CYAF-139 TMP1940CYAF ...
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Timer Components 12.2.1 Prescaler The TMRB0 has a 5-bit prescalar that slows the rate of a clocking source to the counter. The prescalar clock source ( T0) can be selected from fperiph, fperiph/2 and fperiph/4 by programming the PRCK[1:0] ...
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Up-Counter (UC0) The TMRB0 contains a 16-bit binary up-counter, which is driven by a clock selected by the TB0CLK[1:0] field in the TB0MOD register. The clock input to the UC0 is either one of three prescalar outputs ( T4, ...
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TMRB0 TB0RG0 8 high-order bits 0xFFFF_F189 TMRB1 TB1RG0 8 high-order bits 0xFFFF_F199 TMRB2 TB2RG0 8 high-order bits 0xFFFF_F1A9 TMRB3 TB3RG0 8 high-order bits 0xFFFF_F1B9 The Timer registers are write-only registers and cannot be read. 12.2.4 Capture Registers (TB0CP0H/L and TB0CP1H/L) ...
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TMRB0 TB0CP0 8 high-order bits 8 low-order bits 0xFFFF_F18D TMRB1 TB1CP0 8 high-order bits 8 low-order bits 0xFFFF_F19D TMRB2 TB2CP0 8 high-order bits 8 low-order bits 0xFFFF_F1AD TMRB3 TB3CP0 8 high-order bits 8 low-order bits 0xFFFF_F1BD The Capture registers are ...
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Comparators (CP0 and CP1) The TMRB0 contains two 16-bit comparators. The CP0 block compares the output of the up-counter (UC0) with a time constant value in the TB0RG0. The CP1 block compares the output of the UC0 with a ...
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Register Description 7 TB0RUN Name TB0RDE (0xFFFF_F180) Read/Write R/W Reset Value 0 Double Buffering Function 0: Disable 1: Enable Note: Bits 1, 4 and 5 are read as undefined. 7 Name TB1RDE TB1RUN (0xFFFF_F190) Read/Write R/W Reset Value 0 ...
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TB2RUN Name TB2RDE (0xFFFF_F1A0) Read/Write R/W Reset Value 0 Double Buffering Function 0: Disable 1: Enable Note: Bits 1, 4 and 5 are read as undefined. 7 Name TB3RDE TB3RUN (0xFFFF_F1B0) Read/Write R/W Reset Value 0 Double Buffering Function ...
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Name TB0MOD (0xFFFF_F182) Read/Write Reset Value 0 Must be written as 00. Function TMRB0 Mode Register TB0CP0 TB0CPM1 TB0CPM0 R Software Capture triggers capture 00: Disabled 0: Capture 01: TB0IN0 TB0IN1 1: ...
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Name TB1MOD (0xFFFF_F192) Read/Write Reset Value 0 Must be written as 00. Function TMRB1 Mode Register TB1CP0 TB1CPM1 TB1CPM0 R Software Capture triggers capture 00: Disabled 0: Capture 01: TB1IN0 TB1IN1 1: ...
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Name TB2MOD (0xFFFF_F1A2) Read/Write Reset Value 0 Must be written as 00. Function TMRB2 Mode Register TB2CP0 TB2CPM1 TB2CPM0 R Software Capture triggers capture 00: Disabled 0: Capture 01: TB2IN0 TB2IN1 1: ...
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Name TB3MOD (0xFFFF_F1B2) Read/Write Reset Value 0 Must be written as 00. Function TMRB3 Mode Register TB3CP0 TB3CPM1 TB3CPM0 R Software Capture triggers capture 00: Disabled 0: Capture 01: Disabled 1: Don’t ...
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TMRB0 Timer Flip-Flop Control Register 7 Name TB0FFCR (0xFFFF_F183) Read/Write Reset Value 1 Function Must be written as 11. * This field is always read as 11. Note: Capturing the counter value into TB0CP0 via a software capture also generates ...
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TMRB1 Timer Flip-Flop Control Register 7 Name TB1FFCR (0xFFFF_F193) Read/Write Reset Value 1 Function Must be written as 11. * This field is always read as 11. Note: Capturing the counter value into TB1CP0 via a software capture also generates ...
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TMRB2 Timer Flip-Flop Control Register 7 Name TB2FFCR (0xFFFF_F193) Read/Write Reset Value 1 Function Must be written as 11. * This field is always read as 11. Note: Capturing the counter value into TB2CP0 via a software capture also generates ...
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TMRB3 Timer Flip-Flop Control Register 7 Name TB3FFCR (0xFFFF_F1B3) Read/Write Reset Value 1 Function Must be written as 11. * This field is always read as 11. Note: Capturing the counter value into TB3CP0 via a software capture also generates ...
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Operating Modes 12.4.1 16-Bit Interval Timer Mode In the following example, the TMRB0 is used to accomplish periodic interrupt generation. The interval time is set in Timer Register 1 (TB0RG1), and the INTTB01 interrupt is enabled TB0RUN ...
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Programmable Pulse Generation (PPG) Mode The 16-bit PPG mode can be used to generate a square wave with any frequency and duty cycle. The pulse can be high-going and low-going, as determined by the initial setting of the ...
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Figure 12.17 shows a functional diagram of 16-bit PPG mode. Selector TB0IN0 T1 T4 T16 16-Bit Comparator TB0RG0 Selector TB0RG0-WR Register Buffer 0 TB0RUN.TB0RDE Figure 12.17 Functional Diagram of 16-Bit PPG Mode The following is an example of running the ...
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Timing and Measurement Functions Using the Capture Capability The capture capability of the TMRBn provides versatile timing and measurement functions, including the following: One-shot pulse generation using an external trigger pulse Frequency measurement Pulse width measurement Time difference measurement ...