SW00ENB-ZCC Toshiba, SW00ENB-ZCC Datasheet - Page 120

• Manufacturer Part Number: SW00ENB-ZCC
• Description: MCU, MPU & DSP Development Tools CASEWORKS
• Manufacturer: Toshiba

Specifications of SW00ENB-ZCC

• Tool Type: Development Software Support
• Core Architecture: 870
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.2.4
RD
AD[15:0]
ALE
AD[15:0]
ALE
A[23:16]
AD[15:0]
ALE
Read Recovery Time
next external bus cycle. To allow for a read recovery time, one or two dummy cycles can be inserted
between back-to-back bus cycles. (Dummy cycles can only be inserted immediately after a read.)
from the data bus before the next transfer begins. This provides a sufficient time after the RD strobe
for the previous read is deasserted until the address for the next read or write is placed on the address
bus. Figure 8.10 shows bus cycle timing with one and two dummy cycles inserted into bus cycles.
RD
Following an external bus read cycle, a certain recovery time may be required before initiating the
Dummy cycle insertion is programmable in the CS/Wait Controller.
Dummy cycles insert idle cycles between transfers to enable slow off-chip peripherals to remove data
Between an external read and an external read:
Between an external read and an external write:
After an external write:
Figure 8.10 Read Cycle Timing (with Dummy Cycles Inserted)
1 Dummy Cycle
Read Data
Read Data
Dummy
tsys
DATA
tsys
Figure 8.9 Read Recovery Time
TMP1940CYAF-78
ADR
Two Dummy Cycles
Next ADR
Upper Address
2 Dummy Cycles
Dummy
DATA
Programmable
Programmable
No dummy cycle
TMP1940CYAF
ADR
Next ADR